Patents by Inventor Thomas G. Mitchell
Thomas G. Mitchell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962324Abstract: A modified version of the min-sum algorithm (“MSA”) which can lower the error floor performance of quantized LDPC decoders. A threshold attenuated min-sum algorithm (“TAMSA”) and/or threshold offset min-sum algorithm (“TOMSA”), which selectively attenuates or offsets a check node log-likelihood ratio (“LLR”) if the check node receives any variable node LLR with magnitude below a predetermined threshold, while allowing a check node LLR to reach the maximum quantizer level if all the variable node LLRs received by the check node have magnitude greater than the threshold. Embodiments of the present invention can provide desirable results even without knowledge of the location, type, or multiplicity of such objects and can be implemented with only a minor modification to existing decoder hardware.Type: GrantFiled: April 29, 2022Date of Patent: April 16, 2024Assignees: Arrowhead Center, Inc., University of Notre Dame du LacInventors: Homayoon Hatami, David G. Mitchell, Daniel Costello, Thomas Fuja
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Publication number: 20240093287Abstract: The present disclosure relates to compositions and methods for reducing the concentration of extendable free and buried primers relative to amplification product in a sample. The disclosed methods and compositions can be used to reduce or eliminate index hopping in a next generation sequencing (NGS) platform.Type: ApplicationFiled: July 30, 2021Publication date: March 21, 2024Inventors: Keith Robison, Douglas G. Smith, Adam J. Meyer, Andrew J. Mitchell, Alex Plocik, Thomas F. Knight
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Patent number: 10552570Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.Type: GrantFiled: September 10, 2018Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Tsz-mei Ko, Thomas G. Mitchell, Jason D. Morsey, Steven E. Washburn, Patrick M. Williams
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Patent number: 10248753Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC design, generating a blockage circuit section that represents a blockage aggressor circuit in the IC design, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.Type: GrantFiled: October 7, 2016Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Tsz-mei Ko, Thomas G. Mitchell, Jason D. Morsey, Steven E. Washburn, Patrick M. Williams
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Publication number: 20190005182Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Tsz-mei Ko, Thomas G. Mitchell, Jason D. Morsey, Steven E. Washburn, Patrick M. Williams
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Publication number: 20180101636Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.Type: ApplicationFiled: October 7, 2016Publication date: April 12, 2018Inventors: Tsz-mei Ko, Thomas G. Mitchell, Jason D. Morsey, Steven E. Washburn, Patrick M. Williams
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Patent number: 7127689Abstract: A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.Type: GrantFiled: May 28, 2004Date of Patent: October 24, 2006Assignee: International Business Machines CorporationInventors: Paul D. Kartschoke, Thomas G. Mitchell, Norman J. Rohrer, Ronald D. Rose
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Patent number: 6854099Abstract: A method and system for performing parasitic extraction, wherein the method comprises calculating the minimum output impedance for a network-connected component comprising a plurality of ports thereby producing a labeled impedance, estimating the minimum output impedance for every net, comparing the labeled impedance with the estimated impedance, and selecting the net which needs to be extracted based on a ratio of values of the labeled impedance and the estimated impedance. The step of calculating comprises labeling every port with a minimum size of port impedance, a resistance from a port to power, and a minimum capacitance of a port-net inside the network connected component. The step of estimating comprises using a geometry of segments of the net comprising a summation of area and perimeter values of all the segments of the net, or calculating a resistance over a length of a total net versus an average width of the net.Type: GrantFiled: July 1, 2002Date of Patent: February 8, 2005Assignee: International Business Machines CorporationInventors: Lewis W. Dewey, III, Peter A. Habitz, Thomas G. Mitchell
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Publication number: 20040003356Abstract: A method and system for performing parasitic extraction, wherein the method comprises calculating the minimum output impedance for a network-connected component comprising a plurality of ports thereby producing a labeled impedance, estimating the minimum output impedance for every net, comparing the labeled impedance with the estimated impedance, and selecting the net which needs to be extracted based on a ratio of values of the labeled impedance and the estimated impedance. The step of calculating comprises labeling every port with a minimum size of port impedance, a resistance from a port to power, and a minimum capacitance of a port-net inside the network connected component. The step of estimating comprises using a geometry of segments of the net comprising a summation of area and perimeter values of all the segments of the net, or calculating a resistance over a length of a total net versus an average width of the net.Type: ApplicationFiled: July 1, 2002Publication date: January 1, 2004Applicant: International Business Machines CorporationInventors: Lewis W. Dewey, Peter A. Habitz, Thomas G. Mitchell
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Patent number: 6574782Abstract: A structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segments. The invention calculates an up area capacitance component for each of the metal segments by multiplying the area occupied by the metal segments by a wiring density from the wiring density map of an overlying wiring layer over the metal segments and by a capacitance coefficient of the overlying wiring layer. To calculate the down area capacitance component for each of the metal segments, the invention multiplies the area occupied by the metal segments by a wiring density, from the wiring density map of an underlying wiring layer under the metal segments and by a capacitance coefficient of the underlying wiring layer.Type: GrantFiled: November 15, 2000Date of Patent: June 3, 2003Assignee: International Business Machines CorporationInventors: L. William Dewey, III, Peter A. Habitz, Thomas G. Mitchell
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Patent number: D1021072Type: GrantFiled: February 22, 2021Date of Patent: April 2, 2024Assignees: DEKA Products Limited Partnership, CAREFUSION 303, INC.Inventors: Larry B. Gray, Thomas A. Friedrich, Craig A. Dodge, Gregory T. Hulan, Philip T. Pupa, Christopher J. Murray, Edward G. Mitchell
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Patent number: D1021073Type: GrantFiled: February 22, 2021Date of Patent: April 2, 2024Assignees: DEKA Products Limited Partnership, CAREFUSION 303, INC.Inventors: Larry B. Gray, Thomas A. Friedrich, Craig A. Dodge, Gregory T. Hulan, Philip T. Pupa, Christopher J. Murray, Edward G. Mitchell