Abstract: One or more processors receive a breakpoint. The breakpoint is paired with a resume point. One or more processors execute a set of machine instructions on a virtual processor model. One or more processors halt execution of the set of machine instructions on the virtual processor model at the breakpoint. One or more processors execute a fragment of a program instruction on a physical processor. The fragment is logically equivalent to the set of machine instructions between the breakpoint and the resume point. One or more processors load a processed result into the virtual processor model. The processed result results from executing the fragment on the physical processor. One or more processors resume the execution of the set of machine instructions on the virtual processor model at the resume point.

Abstract: A simulation environment benchmarks processors to determine processor performance. A benchmark program is instrumented with a microarchitecture instruction. A first clock cycle indicative of a processor before executing the benchmark program is captured. The benchmark program is executed and a processor return related to the microarchitecture instruction is intercepted. In response to the processor return, a second clock cycle indicative of the processor after executing the benchmark program is captured. The simulation environment determines the performance of the processor from the first clock cycle and the second clock cycle.

Abstract: A simulation environment benchmarks processors to determine processor performance. A benchmark program is instrumented with a microarchitecture instruction. A first clock cycle indicative of a processor before executing the benchmark program is captured. The benchmark program is executed and a processor return related to the microarchitecture instruction is intercepted. In response to the processor return, a second clock cycle indicative of the processor after executing the benchmark program is captured. The simulation environment determines the performance of the processor from the first clock cycle and the second clock cycle.

Abstract: One or more processors receive a breakpoint. The breakpoint is paired with a resume point. One or more processors execute a set of machine instructions on a virtual processor model. One or more processors halt execution of the set of machine instructions on the virtual processor model at the breakpoint. One or more processors execute a fragment of a program instruction on a physical processor. The fragment is logically equivalent to the set of machine instructions between the breakpoint and the resume point. One or more processors load a processed result into the virtual processor model. The processed result results from executing the fragment on the physical processor. One or more processors resume the execution of the set of machine instructions on the virtual processor model at the resume point.

Abstract: One or more processors receive a breakpoint. The breakpoint is paired with a resume point. One or more processors execute a set of machine instructions on a virtual processor model. One or more processors halt execution of the set of machine instructions on the virtual processor model at the breakpoint. One or more processors execute a fragment of a program instruction on a physical processor. The fragment is logically equivalent to the set of machine instructions between the breakpoint and the resume point. One or more processors load a processed result into the virtual processor model. The processed result results from executing the fragment on the physical processor. One or more processors resume the execution of the set of machine instructions on the virtual processor model at the resume point.

Abstract: One or more processors receive a breakpoint. The breakpoint is paired with a resume point. One or more processors execute a set of machine instructions on a virtual processor model. One or more processors halt execution of the set of machine instructions on the virtual processor model at the breakpoint. One or more processors execute a fragment of a program instruction on a physical processor. The fragment is logically equivalent to the set of machine instructions between the breakpoint and the resume point. One or more processors load a processed result into the virtual processor model. The processed result results from executing the fragment on the physical processor. One or more processors resume the execution of the set of machine instructions on the virtual processor model at the resume point.

Abstract: A simulation environment benchmarks processors to determine processor performance. A benchmark program is instrumented with a microarchitecture instruction. A first clock cycle indicative of a processor before executing the benchmark program is captured. The benchmark program is executed and a processor return related to the microarchitecture instruction is intercepted. In response to the processor return, a second clock cycle indicative of the processor after executing the benchmark program is captured. The simulation environment determines the performance of the processor from the first clock cycle and the second clock cycle.

Abstract: A simulation environment benchmarks processors to determine processor performance. A benchmark program is instrumented with a microarchitecture instruction. A first clock cycle indicative of a processor before executing the benchmark program is captured. The benchmark program is executed and a processor return related to the microarchitecture instruction is intercepted. In response to the processor return, a second clock cycle indicative of the processor after executing the benchmark program is captured. The simulation environment determines the performance of the processor from the first clock cycle and the second clock cycle.

Abstract: A method is disclosed for balancing the requirements of high availability achieved by redundant active components and power saving achieved by less active components. The requirement for high availability can be expressed by the recovery time objective (RTO) which specifies the amount of time it takes to recover from a failure in the system. Based on the configured RTO, the system configures the most appropriate power mode.

Abstract: A system and method are disclosed for balancing the requirements of high availability achieved by redundant active components and power saving achieved by less active components. The requirement for high availability can be expressed by the recovery time objective (RTO) which specifies the amount of time it takes to recover from a failure in the system. Based on the configured RTO, the system configures the most appropriate power mode.

Abstract: A system and method are disclosed for balancing the requirements of high availability achieved by redundant active components and power saving achieved by less active components. The requirement for high availability can be expressed by the recovery time objective (RTO) which specifies the amount of time it takes to recover from a failure in the system. Based on the configured RTO, the system configures the most appropriate power mode.

Abstract: An example of the invention classifies disks drives based on their purpose and associating power-saving policies in multiple classes. The system implements Power On Demand, where a reduced power mode is enabled for every individual component of a storage subsystem. In addition, an embodiment of this invention extends a few power modes used in the prior art and allows almost infinite number of power modes when instructing a disk drive (via its I/O interface such as a SCSI or fibre channel interface) to enter a certain power saving mode. Furthermore, an embodiment of invention teaches a system and methods to save power in a disk system comprising a plurality of disk controllers and a plurality of disk drives, arranged in a plurality of arrays, where each array includes several (e.g., 4-16) disk drives.

Abstract: An example of the invention classifies disks drives based on their purpose and associating power-saving policies in multiple classes. The system implements Power On Demand, where a reduced power mode is enabled for every individual component of a storage subsystem. In addition, an embodiment of this invention extends a few power modes used in the prior art and allows almost infinite number of power modes when instructing a disk drive (via its I/O interface such as a SCSI or fiber channel interface) to enter a certain power saving mode. Furthermore, an embodiment of invention teaches a system and methods to save power in a disk system comprising a plurality of disk controllers and a plurality of disk drives, arranged in a plurality of arrays, where each array includes several (e.g., 4-16) disk drives.