Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.

Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.

Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.

Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system.

Abstract: A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

Abstract: A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

Abstract: The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.

Abstract: A method for a continuous mutual extended processor self-test is provided. The method is implemented by a system including a plurality of cores. The system sets an operating condition for the continuous mutual extended processor self-test. An assist processor of the plurality of cores executes a test program that implements the continuous mutual extended processor self-test on a core under test of the plurality of cores. The system determines a pattern and a response during the test program execution and repeats the test program until the test program has finished or failed.

Abstract: The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.

Abstract: A method, computer program product and/or system is disclosed. According to an aspect of this invention, a device under test (DUT) is switched to a functional test mode. In some embodiments of the present invention, the DUT receives a general scan design (GSD) pattern while in the functional test mode. In some embodiments, the DUT executes a first functional test corresponding to the GSD pattern. In yet other embodiments, the DUT further comprises a state machine that controls the execution of the first functional test. The DUT may further store the output address, the output data, and the status to an address register, a data register, and a status register, respectively and/or send the output address, the output data, and the status to an address register to an automatic testing equipment (ATE).

Abstract: Embodiments of the invention are directed to a built-in self-test system for an electronic circuit. The system includes a memory having two or more base seeds stored thereon. The system further includes seed generation logic configured to generate, based at least in part on the two or more base seeds, a plurality of generated seeds. The generated seeds can be constructed from the base seeds such that each of the generated seeds encodes a test pattern that satisfies a functional constraint. A finite state machine is configured to generate, based on the plurality of generated seeds, a sequence of constrained pseudorandom test patterns. A test controller is operable to place the electronic circuit into a test mode based on the constrained pseudorandom test pattern.

Abstract: A functional testing high-speed serial link system includes a testing controller that generates a functional testing program, and a device under test (DUT) that receives the functional testing program. The DUT includes a first logic circuit array that generates first results in response to executing the functional test program. The system also includes a supporting chip that receives the functional testing program. The supporting chip includes a second logic circuit array that generates second results in response to executing the functional test program. A physical data link establishes signal communication between the DUT and the supporting chip. The testing controller diagnoses the physical link based on a comparison between expected diagnostic results associated with the functional testing program, and at least one of the first results and the second results.

Abstract: A method for a continuous mutual extended processor self-test is provided. The method is implemented by a system including a plurality of cores. The system sets an operating condition for the continuous mutual extended processor self-test. An assist processor of the plurality of cores executes a test program that implements the continuous mutual extended processor self-test on a core under test of the plurality of cores. The system determines a pattern and a response during the test program execution and repeats the test program until the test program has finished or failed.

Abstract: A functional testing high-speed serial link system includes a testing controller that generates a functional testing program, and a device under test (DUT) that receives the functional testing program. The DUT includes a first logic circuit array that generates first results in response to executing the functional test program. The system also includes a supporting chip that receives the functional testing program. The supporting chip includes a second logic circuit array that generates second results in response to executing the functional test program. A physical data link establishes signal communication between the DUT and the supporting chip. The testing controller diagnoses the physical link based on a comparison between expected diagnostic results associated with the functional testing program, and at least one of the first results and the second results.

Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.

Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.

Abstract: A method, computer program product and/or system is disclosed. According to an aspect of this invention, a device under test (DUT) is switched to a functional test mode. In some embodiments of the present invention, the DUT receives a general scan design (GSD) pattern while in the functional test mode. In some embodiments, the DUT executes a first functional test corresponding to the GSD pattern. In yet other embodiments, the DUT further comprises a state machine that controls the execution of the first functional test. The DUT may further store the output address, the output data, and the status to an address register, a data register, and a status register, respectively and/or send the output address, the output data, and the status to an address register to an automatic testing equipment (ATE).

Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.

Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.

Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.