Abstract: An illuminated flag, the flag includes a first layer of flag, a second layer of flag and a spacer separating the first and second flag layers to form an optical cavity between the first and second flag layers. A light source is contained within the optical cavity to illuminate the first and second layers. A light distribution element between the light source and layers of the flag distributes the light uniformly upon the inside of the layers. This illumination from within the flag provides a substantially uniform glow to the exterior of the flag. The flag can be supported by a standard flag pole and is able to move in a breeze.

Abstract: An illumination device used to replace fluorescent light tubes. The illumination device comprises an LED light strip, a diffusion tube surrounding the LED light strip, and an end cap mounted on each end of the tube. Electrical connectors integrated with the end caps and make electrical connection with the LED light strip. The device may be hermetically sealed, use LED's to rectify the current, have a filament simulator with or without a visual indicator, two-sided or multi-sided light strips, light diffusing end caps and be filled with a life-extending gas. The illumination device results in an LED light tube with improved lighting uniformity, reduced energy consumption, improved ease of use and longer operating life.

Abstract: A pearl comprised of cremated remains surrounded by nacre. The cremated remains may be from any person or pet. The pearls containing cremated remains can be incorporated into fine jewelry to create ageless, beautiful keepsakes for the remembrance of deceased loved ones.

Abstract: An illuminated pop-up candy comprising a housing, cap, moveable candy, moveable illumination system, and switching mechanism. The candy is able to translate and rotate along the length of the housing by the application of pressure to either the candy or the illumination system. The illumination system is switched on and off by touch or translation of the illumination along said housing.

Abstract: A common-path, point-diffraction, phase-shifting interferometer uses a half wave plate having a diffractive element, such as pin hole. A coherent, polarized light source simultaneously generates a reference beam from the diffractive element and an object beam from remaining portions of the light going through the half wave plate. The reference beam has a nearly spherical wavefront. Each of the two beams possesses a different polarization state. The object and reference beams are then independently phase modulated by a polarization sensitive phase modulator that shifts phase an amount depending on applied voltage and depending on polarization state of the incident light. A polarizer is then used to provide the object and reference beams in the same polarization state with equal intensities so they can interfere to create an interferogram with near unity contrast.

Abstract: A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.

Abstract: A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.

Abstract: A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plane parallel to the surface of the substrate and a c-direction normal to the surface of the substrate. Generally, the method includes providing the substrate, growing the HTS film on the substrate and, after the HTS film has been grown, inducing into the HTS film a residual compressive strain the a-b plane and a residual tensile strain into the c-direction.

Abstract: A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.

Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of a chip at increased frequencies.

Abstract: The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.

Abstract: An apparatus and method utilize vacuum injected molding of a liquid in a plurality of mold cells for solidification therein. An injection head includes spaced apart vacuum and injection slots positionable atop a mold plate in flow communication with the mold cells therein. Relative axial sliding is effected between the injection head and the mold plate for sequentially evacuating gas from the mold cells using a continuous vacuum followed in turn by sequentially injecting into the evacuated mold cells the liquid from a continuous source thereof. Sliding of the injection head over the mold plate automatically provides self valving for sequentially evacuating and filling the mold cells from the same side of the mold plate. In a preferred embodiment, the vacuum and injection slots are linked together at the mold plate so that surface tension of the liquid restrains flow of the liquid from the injection slot to the vacuum slot while allowing gas flow therebetween for effecting the vacuum in the mold cells.

Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.