Patents by Inventor Thomas Gray
Thomas Gray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977766Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.Type: GrantFiled: February 28, 2022Date of Patent: May 7, 2024Assignee: NVIDIA CorporationInventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
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Publication number: 20240115211Abstract: Disclosed are systems and methods for generating graphical displays of analyte data and/or health information. In some implementations, the graphical displays are generating based on a self-referential dataset that are modifiable based on identified portions of the data. The modified graphical displays can indicate features in the analyte data of a host.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Esteban CABRERA, JR., Lauren Danielle ARMENTA, Scott M. BELLIVEAU, Jennifer BLACKWELL, Leif N. BOWMAN, Rian DRAEGER, Arturo GARCIA, Timothy Joseph GOLDSMITH, John Michael GRAY, Andrea Jean JACKSON, Apurv Ullas KAMATH, Katherine Yerre KOEHLER, Paul KRAMER, Aditya Sagar MANDAPAKA, Michael Robert MENSINGER, Sumitaka MIKAMI, Gary A. MORRIS, Hemant Mahendra NIRMAL, Paul NOBLE-CAMPBELL, Philip Thomas PUPA, Eli REIHMAN, Peter C. SIMPSON, Brian Christopher SMITH, Atiim Joseph WILEY
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Patent number: 11953429Abstract: Systems and methods of the present disclosure include at least one building component detection sensor device configured to be deployed within (or proximate to) a building comprised of a plurality of building components. The at least one building component detection sensor device is configured to detect data relating to at least one building component of the plurality of building components. In addition, a building component property determination system includes a processor configured to execute instructions stored in memory to determine one or more properties of the at least one building component based at least in part on the data detected by the at least one building component detection sensor device.Type: GrantFiled: May 8, 2023Date of Patent: April 9, 2024Assignee: United Services Automobile Association (USAA)Inventors: Emily Margaret Gray, Daniel Christopher Bitsis, Jr., Qunying Kou, Robert Wiseman Simpson, Manfred Amann, Donnette Moncrief Brown, Eric David Schroeder, Meredith Beveridge, Michael J. Maciolek, Bobby Lawrence Mohs, Brian F. Shipley, Justin Dax Haslam, Ashley Raine Philbrick, Yevgeniy Viatcheslavovich Khmelev, Oscar Guerra, Jeffrey Neal Pollack, Janelle Denice Dziuk, Ryan Thomas Russell, David Patrick Dixon
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Patent number: 11953953Abstract: An avionics unit assembly for an aircraft can include an avionics unit (e.g., an underwater locator device, “ULD”), and a battery to power the avionics unit. The avionics unit assembly can further include a housing that encases the avionics unit and the battery. The housing includes a vent port for exhausting an emission from the housing during a failure of the avionics unit. The avionics unit assembly can further include one or more of a suppressor that filters the emission, a shield element that is resistant to chemical and/or thermal effects of the emission, and a bracket for mounting the avionics unit to a surface. A method integrating the avionics unit assembly onto a forward aircraft bulkhead at a mount location under an aircraft radome and for manufacturing the avionics unit, and an aircraft including the avionics unit are also described.Type: GrantFiled: September 27, 2018Date of Patent: April 9, 2024Assignee: THE BOEING COMPANYInventors: Ramon L. Cuenca, Shellini P. Dowell, Thomas A. Jessett, Fadl I. Khalil, Warren S. Ng, Scott B. Vacknitz, Collis M. Walker, Archibald A. Gray, James C. Russell, Charles O. Adler
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Patent number: 11943876Abstract: Pre-connected analyte sensors are provided. A pre-connected analyte sensor includes a sensor carrier attached to an analyte sensor. The sensor carrier includes a substrate configured for mechanical coupling of the sensor to testing, calibration, or wearable equipment. The sensor carrier also includes conductive contacts for electrically coupling sensor electrodes to the testing, calibration, or wearable equipment.Type: GrantFiled: October 23, 2018Date of Patent: March 26, 2024Assignee: DexCom, Inc.Inventors: Jason Halac, John Charles Barry, Becky L. Clark, Chris W. Dring, John Michael Gray, Kris Elliot Higley, Jeff Jackson, David A. Keller, Ted Tang Lee, Jason Mitchell, Kenneth Pirondini, David Rego, Ryan Everett Schoonmaker, Peter C. Simpson, Craig Thomas Gadd, Kyle Thomas Stewart, John Stanley Hayes
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Patent number: 11931188Abstract: Disclosed are systems and methods for generating graphical displays of analyte data and/or health information. In some implementations, the graphical displays are generating based on a self-referential dataset that are modifiable based on identified portions of the data. The modified graphical displays can indicate features in the analyte data of a host.Type: GrantFiled: September 21, 2021Date of Patent: March 19, 2024Assignee: Dexcom, Inc.Inventors: Esteban Cabrera, Jr., Lauren Danielle Armenta, Scott M. Belliveau, Jennifer Blackwell, Leif N. Bowman, Rian Draeger, Arturo Garcia, Timothy Joseph Goldsmith, John Michael Gray, Andrea Jean Jackson, Apurv Ullas Kamath, Katherine Yerre Koehler, Paul Kramer, Aditya Sagar Mandapaka, Michael Robert Mensinger, Sumitaka Mikami, Gary A Morris, Hemant Mahendra Nirmal, Paul Noble-Campbell, Philip Thomas Pupa, Eli Reihman, Peter C. Simpson, Brian Christopher Smith, Atiim Joseph Wiley
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Publication number: 20240067326Abstract: An aircraft wing is disclosed having a main fixed wing portion and a wing tip device at a tip thereof. The wing tip device is configurable between a flight configuration and a ground configuration, in which ground configuration the wing tip device is moved away from the flight configuration such that the span of the aircraft wing is reduced. A hinge arrangement connects the main fixed wing portion and the wing tip device and enables the wing tip device to rotate between the ground configuration and the flight configuration. The hinge arrangement protrudes beyond an outer surface of the main fixed wing portion and wing tip device. A fairing covers at least part of the hinge arrangement on at least a suction side of the wing.Type: ApplicationFiled: August 30, 2023Publication date: February 29, 2024Inventors: Oliver FAMILY, Robert MILLS, Christopher GRAY, Thomas WILSON
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Patent number: 11784835Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.Type: GrantFiled: September 21, 2021Date of Patent: October 10, 2023Assignee: NVIDIA CORP.Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
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Publication number: 20230315651Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
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Publication number: 20230297269Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile’s local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50x for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10x.Type: ApplicationFiled: February 28, 2022Publication date: September 21, 2023Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O’Connor
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Publication number: 20230297499Abstract: A mapper within a single-level memory system may facilitate memory localization to reduce the energy and latency of memory accesses within the single-level memory system. The mapper may translate a memory request received from a processor for implementation at a data storage entity, where the translating identifies a data storage entity and a starting location within the data storage entity where the data associated with the memory request is located. This data storage entity may be co-located with the processor that sent the request, which may enable the localization of memory and significantly improve the performance of memory usage by reducing an energy of data access and increasing data bandwidth.Type: ApplicationFiled: January 21, 2022Publication date: September 21, 2023Inventors: William James Dally, Stephen William Keckler, Carl Thomas Gray, James Michael O’Connor
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Publication number: 20230275068Abstract: Embodiments of the present disclosure relate to memory stacked on processor for high bandwidth. Systems and methods are disclosed for providing a one-level memory for a processing system by stacking bulk memory on a processor die. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles, where each tile includes a processing unit, mapper, and tile network. Each memory die includes multiple memory tiles. The processing tile is coupled to each memory tile that is above or below the processing tile. The vertically aligned memory tiles comprise the local memory block for the processing tile. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
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Publication number: 20220271951Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.Type: ApplicationFiled: February 24, 2021Publication date: August 25, 2022Applicant: NVIDIA Corp.Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
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Publication number: 20220271952Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.Type: ApplicationFiled: September 21, 2021Publication date: August 25, 2022Applicant: NVIDIA Corp.Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
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Patent number: 11411563Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.Type: GrantFiled: February 24, 2021Date of Patent: August 9, 2022Assignee: NVIDIA Corp.Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
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Publication number: 20220224694Abstract: Described embodiments provide systems and methods for resource appropriation in a multi-tenant environment using risk and value modeling. A resource server can provide a plurality of applications access to a plurality of resources in response to requests from clients based in part on risk scores and value scores. The resource server can generate and execute a risk model and a value model to determine a risk score and a value score for each of the applications. The resource server can use the risk and value scores to determine access to a particular resource for a requested application. The resource server can assign a first allocation of resource tokens to an application. The resource tokens can correspond to access privileges to plurality of resources. The resource server can dynamically modify the resource allocation for applications responsive to changes to a risk score or value score of a respective application.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Applicant: Citrix Systems, Inc.Inventors: Alok Aggarwal, Josh Thomas Gray, Darren Gilroy
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Patent number: 11349803Abstract: Described embodiments provide systems and methods for resolving Domain Name Service (DNS) requests. An authoritative DNS server may receive, from a recursive resolver, a DNS request to resolve a query on behalf of a client. The authoritative DNS server may determine whether the recursive resolver is classified as a non-client representative resolver or a client representative resolver. The authoritative DNS server may identify a redirect server based on the recursive resolver classified as the non-client representative resolver or the resolved server based on the recursive resolver classified as the client representative resolver. The authoritative DNS server may transmit, to the recursive resolver, a response to the DNS request including an address of one of the redirect server or the resolved server.Type: GrantFiled: September 18, 2020Date of Patent: May 31, 2022Assignee: Citrix Systems, Inc.Inventors: Josh Thomas Gray, Steven Lyons
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Patent number: 11302291Abstract: Systems, methods, and computer-readable media are disclosed for systems and methods for device agnostic user interface generation. Example methods include receiving a request for content from a device, determining first data representing a first device characteristic of the device, and determining an intended viewing distance value associated with the first data. Some methods include determining, using the intended viewing distance value, a first value for the device, the first value representing a baseline density-independent number of pixels, determining first content using the first value, and sending the first content to the device, where the first content is to be rendered at the device.Type: GrantFiled: November 27, 2019Date of Patent: April 12, 2022Assignee: Amazon Technologies, Inc.Inventors: Bradley McNally, Kynan Dylan Antos, Jennifer Lynne Cotton, Jonathan Mongan, Sahil Ahmed Yousif Anand, Timothy Thomas Gray, Ryan Long
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Patent number: 11297067Abstract: Described embodiments provide systems and methods for resource appropriation in a multi-tenant environment using risk and value modeling. A resource server can provide a plurality of applications access to a plurality of resources in response to requests from clients based in part on risk scores and value scores. The resource server can generate and execute a risk model and a value model to determine a risk score and a value score for each of the applications. The resource server can use the risk and value scores to determine access to a particular resource for a requested application. The resource server can assign a first allocation of resource tokens to an application. The resource tokens can correspond to access privileges to plurality of resources. The resource server can dynamically modify the resource allocation for applications responsive to changes to a risk score or value score of a respective application.Type: GrantFiled: May 13, 2019Date of Patent: April 5, 2022Assignee: Citrix Systems, Inc.Inventors: Alok Aggarwal, Josh Thomas Gray, Darren Gilroy
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Patent number: 11250201Abstract: Systems and methods for presenting a user interface in a first mode and a second mode based on detection of a touch gesture is described herein. In some embodiments, a first user interface may be presented on an electronic device's display. The first user interface may include a list of items, which may be formatted such that they are optimally viewable from a first distance away from the display. In response to detecting a touch gesture, such as a scrolling gesture, a second user interface may be presented including the list of items, which may be formatted such that they are optimally viewed from a second distance. For example, the first user interface may be optimally viewable from a distance of approximately seven to ten feet from the display. As another example, the second user interface may optimally viewable from a distance of approximately one to three feet.Type: GrantFiled: June 14, 2016Date of Patent: February 15, 2022Assignee: Amazon Technologies, Inc.Inventors: Timothy Thomas Gray, Thomas Irvine Nelson, Jae Pum Park, Shilpan Bhagat