Patents by Inventor Thomas Grebinski

Thomas Grebinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow
    Patent number: 8266571
    Abstract: The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: September 11, 2012
    Assignee: Oasis Tooling, Inc.
    Inventors: David Chapman, Thomas Grebinski
  • Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow
    Patent number: 7685545
    Abstract: The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: March 23, 2010
    Assignee: Oasis Tooling, Inc.
    Inventors: David Chapman, Thomas Grebinski
  • Methods and Devices for Independent Evaluation of Cell Integrity, Changes and Origin in Chip Design for Production Workflow
    Publication number: 20090307640
    Abstract: The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data.
    Type: Application
    Filed: August 5, 2009
    Publication date: December 10, 2009
    Applicant: Oasis Tooling, Inc.
    Inventors: David Chapman, Thomas Grebinski
  • METHODS AND DEVICES FOR INDEPENDENT EVALUATION OF CELL INTEGRITY, CHANGES AND ORIGIN IN CHIP DESIGN FOR PRODUCTION WORKFLOW
    Publication number: 20090307639
    Abstract: The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data.
    Type: Application
    Filed: June 10, 2009
    Publication date: December 10, 2009
    Applicant: Oasis Tooling, Inc.
    Inventors: David Chapman, Thomas Grebinski
  • Ultra-flat reflective MEMS optical elements
    Publication number: 20060109534
    Abstract: The present invention relates to producing ultra flat micro surfaces suitable, for instance, for micro-mirrors. In particular, it relates to low pressure chemical mechanical planarization (CMP) of a partially cured sacrificial layer.
    Type: Application
    Filed: November 1, 2005
    Publication date: May 25, 2006
    Applicant: Micronic Laser Systems AB
    Inventor: Thomas Grebinski