Abstract: System and method for carrying out a process on an integrated circuit. The method includes reading a data key including subkeys, determining a process parameter set using a parameter directory in a manner dependent on the data key read in, and setting the parameters required for the process in accordance with the process parameter set determined. The parameter directory includes rule keys each having subkeys, which are each assigned predeterminable values from a plurality of values, and at least one subkey is assigned a wildcard, and a plurality of process parameter sets each respectively assigned at least one rule key. The step of determining a parameter set includes comparing the data key read in with the rule keys stored in the parameter directory, determining the rule key(s) whose subkeys match those of the data key read in, and outputting the process parameter set(s) assigned to the rule key(s) determined.

Abstract: System and method for carrying out a process on an integrated circuit. The method includes reading a data key including subkeys, determining a process parameter set using a parameter directory in a manner dependent on the data key read in, and setting the parameters required for the process in accordance with the process parameter set determined. The parameter directory includes rule keys each having subkeys, which are each assigned predeterminable values from a plurality of values, and at least one subkey is assigned a wildcard, and a plurality of process parameter sets each respectively assigned at least one rule key. The step of determining a parameter set includes comparing the data key read in with the rule keys stored in the parameter directory, determining the rule key(s) whose subkeys match those of the data key read in, and outputting the process parameter set(s) assigned to the rule key(s) determined.

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: An electronic calibration component for calibrating a tester device is described. The calibration component has a signal input, to which a tester channel to be calibrated can be connected, and a phase difference circuit. The phase difference circuit can be connected to the signal input and can be connected to a reference clock signal. As a result, a phase difference information item is determined between a cyclic signal applied to the signal input and the reference clock signal. The electronic calibration component also has an output device in order to output the phase difference information item. The latter is received by a tester device that can be connected to the calibration component via tester channels. The tester device has a delay device that is connected to the tester channel in order to delay signals to be transmitted on the tester channel on the basis of the phase difference information item.

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: An electronic calibration component for calibrating a tester device is described. The calibration component has a signal input, to which a tester channel to be calibrated can be connected, and a phase difference circuit. The phase difference circuit can be connected to the signal input and can be connected to a reference clock signal. As a result, a phase difference information item is determined between a cyclic signal applied to the signal input and the reference clock signal. The electronic calibration component also has an output device in order to output the phase difference information item. The latter is received by a tester device that can be connected to the calibration component via tester channels. The tester device has a delay device that is connected to the tester channel in order to delay signals to be transmitted on the tester channel on the basis of the phase difference information item.