Abstract: A shallow draft boat having a boat hull that allows for stability, maneuverability, and speed while needing only inches of draft. The hull generally includes a ski, a bottom shell, a left and right chine and a bow wrapper.

Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is generated based on the phase error signals, the difference value indicating a difference between the number of the phase error signals having the first state and a number of the phase error signals having the second state. The difference value is transferred to a processor which is programmed to determine whether the difference value exceeds a first threshold and, if so, to adjust the phase of the first clock signal.

Abstract: A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.

Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: The novel dump body enables a dump truck to carry large, packaged loads and large, loose loads. The dump body includes a containment base having a bottom and a plurality of sides. The dump body further includes a dumping mechanism formed in one of the plurality of sides for releasing loose materials when the containment base is tipped. Finally, the dump body includes at least one side door pivotably attached to the containment base and covering a first opening formed in at least a portion of one of the plurality of sides. The side door permits packaged loads to be loaded onto the dump truck, wherein the sides on the dump truck normally prohibit the carrying of this type of load.

Abstract: The present invention is a novel dump body for a dump truck, which enables the dump truck to carry large, packaged loads and large, loose loads. The dump body includes a containment base having a bottom and a plurality of sides. The dump body further includes a dumping means formed in one of the plurality of sides for releasing loose materials when the containment base is tipped. Finally, the dump body includes at least one side door pivotably attached to the containment base and covering a first opening formed in at least a portion of one of the plurality of sides. The side door permits packaged loads to be loaded onto the dump truck, wherein the sides on the dump truck normally prohibit the carrying of this type of load.