Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to a control register, the data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers.

Abstract: A program register is coupled between a data bus N bits wide and an address but N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. for certain instructions, the address bus is be utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter depending on the type of instruction being executed.