Patents by Inventor Thomas H. Kinsley

Thomas H. Kinsley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960717
    Abstract: Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: April 16, 2024
    Inventors: Thomas H. Kinsley, Matthew A. Prather
  • Patent number: 11955457
    Abstract: Semiconductor assemblies and packages using edge stacking and associated systems and methods are disclosed herein. A semiconductor package may include (1) a base substrate having a base surface, (2) one or more dies attached over the base surface, and (3) a mold material encapsulating the base substrate and the one or more dies. The package may further include connectors on a side surface thereof, wherein the connectors are electrically coupled to the base substrate and/or the one or more dies. The connectors may be further configured to electrically couple the package to one or more neighboring semiconductor packages and/or electrical circuits.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Publication number: 20240111707
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 4, 2024
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Publication number: 20240096425
    Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.
    Type: Application
    Filed: July 5, 2023
    Publication date: March 21, 2024
    Inventors: Baekkyu Choi, Fuad Badrieh, Thomas H. Kinsley
  • Publication number: 20240077926
    Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.
    Type: Application
    Filed: July 5, 2023
    Publication date: March 7, 2024
    Inventors: Baekkyu Choi, Thomas H. Kinsley, Fuad Badrieh
  • Patent number: 11921560
    Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, Baekkyu Choi, Fuad Badrieh
  • Patent number: 11922990
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 5, 2024
    Inventors: Matthew A. Prather, Thomas H. Kinsley
  • Publication number: 20240005978
    Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 4, 2024
    Inventors: Fuad Badrieh, Thomas H. Kinsley, Baekkyu Choi
  • Patent number: 11855048
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 26, 2023
    Inventors: Thomas H. Kinsley, George E. Pax
  • Patent number: 11789890
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: October 17, 2023
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Patent number: 11783882
    Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 10, 2023
    Inventors: Matthew A. Prather, Thomas H. Kinsley
  • Patent number: 11763874
    Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Thomas H. Kinsley, Fuad Badrieh
  • Patent number: 11749357
    Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Fuad Badrieh, Thomas H. Kinsley
  • Patent number: 11726541
    Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Thomas H. Kinsley, Fuad Badrieh
  • Patent number: 11721742
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards
  • Patent number: 11721386
    Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fuad Badrieh, Thomas H. Kinsley, Baekkyu Choi
  • Patent number: 11721401
    Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Fuad Badrieh, Thomas H. Kinsley
  • Patent number: 11715725
    Abstract: Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Publication number: 20230118893
    Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Thomas H. Kinsley, Baekkyu Choi, Fuad Badrieh
  • Patent number: 11589480
    Abstract: Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. An apparatus may have a printed circuit board (PCB) having an edge connector. At least one integrated circuit device may be disposed on a surface of the PCB. A tubular heat spreader may be disposed along an edge of the PCB opposite the edge connector.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards