Abstract: The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings.

Abstract: The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings.

Abstract: A device includes an integrated circuit (IC) carrier for a semiconductor device, and a coating on the IC carrier. In the presence of an electrical field or a magnetic field, the coating includes a first functional group that attracts anions and a second functional group that attracts cations.

Abstract: A device includes an integrated circuit (IC) carrier for a semiconductor device, and a coating on the IC carrier. In the presence of an electrical field or a magnetic field, the coating includes a first functional group that attracts anions and a second functional group that attracts cations.

Abstract: The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings.

Abstract: A packaged semiconductor device having a package substrate that includes a plurality of electrical contacts on a first major surface and a die positioned on a second major surface. Each of the plurality of electrical contacts includes a perimeter portion. A first subset of the electrical contacts have more than fifty percent of the perimeter portion bounded by a solder mask. A second subset of the electrical contacts have less than fifty percent of the perimeter portion bounded by a solder mask. The die is positioned over only the first subset of the electrical contacts.

Abstract: A mechanism is provided by which delamination of a substrate of a system-in-package is prevented. A mold lock feature is provided within the substrate that allows the mold compound forming the encapsulant to flow into the mold lock feature, thereby anchoring the encapsulant to the substrate. The mold lock features can be provided in areas of the substrate where higher stresses due to component configuration are predicted. Aspects of the present invention provide for a method of forming the mold lock features that is compatible with current methods of forming laminate substrates, and thereby do not require an increase in cost for manufacturing the substrate.

Abstract: A mechanism is provided by optically inspectable surface mount bonding of no-leads packages is enhanced. Embodiments of the present invention use a lead frame within the no-leads package that provides a plated surface not only along the bottom of the package but also in a direction substantially parallel to the sides of the package. Since the plated surface has a greater affinity for solder during a reflow process than does the bare metal of the lead frame, toe fillets have a greater chance of forming in a manner that can be optically inspected during a test for quality of the bonding of the package to a printed circuit board. In addition, a mold chase that conforms to the shape of the lead frame is used to prevent mold compound from adhering to the portions of the lead frame external to the package that are used as electrical contacts.

Abstract: An apparatus and method uses a die having at least one perimeter side with multiple pads. A structure is positioned between the at least one perimeter side and the multiple pads having multiple layers within the die. The structure functions as both a strain gauge and a crack stop. The structure arrests cracks from propagating from the at least one perimeter side to an interior of the die and provides an electrical resistance value as a function of an amount of strain existing where the structure is positioned. In another form the structure is implemented on a substrate such as a printed circuit board rather than in a semiconductor die.

Abstract: An apparatus and method uses a die having at least one perimeter side with multiple pads. A structure is positioned between the at least one perimeter side and the multiple pads having multiple layers within the die. The structure functions as both a strain gauge and a crack stop. The structure arrests cracks from propagating from the at least one perimeter side to an interior of the die and provides an electrical resistance value as a function of an amount of strain existing where the structure is positioned. In another form the structure is implemented on a substrate such as a printed circuit board rather than in a semiconductor die.

Abstract: A solder system includes a lead (Pb) indicator and a solder flux. A method for forming a semiconductor device includes providing a carrier, applying the solder system to the carrier, coupling the terminal to the carrier via the solder system, melting the solder system to attach the terminal to the carrier and form a completed semiconductor device, and determining if the completed semiconductor device has a different predetermined property from the solder system.

Abstract: Improved electro-mechanical connections between a packaged semiconductor die (12) and a printed circuit board (60) with reduced standoff height and pitch are created by the use of a non-planar semiconductor package substrate (24) having a surface with angulated portions. Electrically conductive surfaces (54) are formed over the angulated portions. In one embodiment, the electrically conductive surfaces may be formed by forming an electrically conductive surface (54) over a non-planar or angulated package substrate (42). The electrically conductive angulated surfaces improve reliability of solder joints (70) upon connecting the packaged semiconductor die to the printed circuit board (60). The gaps within the solder mask openings provide a thin profile and improved pitch. In one form, the die may be on a same side of the package as the angulated substrate surface.

Abstract: Improved electro-mechanical connections between a packaged semiconductor die (12) and a printed circuit board (60) with reduced standoff height and pitch are created by the use of a non-planar semiconductor package substrate (24) having a surface with angulated portions. Electrically conductive surfaces (54) are formed over the angulated portions. In one embodiment, the electrically conductive surfaces may be formed by forming an electrically conductive surface (54) over a non-planar or angulated package substrate (42). The electrically conductive angulated surfaces improve reliability of solder joints (70) upon connecting the packaged semiconductor die to the printed circuit board (60). The gaps within the solder mask openings provide a thin profile and improved pitch. In one form, the die may be on a same side of the package as the angulated substrate surface.

Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.

Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.

Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.