Abstract: A three-stage differential ring oscillator circuit has a first differential stage, a second differential stage, and a third differential stage and generates six phases (two in each stage) used to form differential in-phase and quadrature-phase clock signals. A cross coupled inverter pair couples the first stage output signals. A second cross coupled inverter pair couples the second stage output signals. A third cross coupled inverter pair couples the third stage output signals. A first interpolator generates a first quadrature-phase clock signal using two phases (one from the positive portion of the second stage and one from the negative portion of the third stage) and a second interpolator generates a second quadrature-phase clock signal using two phases (one from the negative portion of the second stage and one from the positive portion of the third stage). Two phases from the first differential stage form the differential pair of in-phase clock signals.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: An internal state machine controller in an integrated circuit containing a cryptographic implementation independently tests and verifies each of the encryption and decryption algorithms and modes within the implementation with minimal processor intervention. The cryptographic implementation automatically generates all input data and exercises all feedback modes independent of the core processor. Eliminating external test vectors results in a device less expensive to manufacture and verify. Since the cryptographic implementation tests are performed independent of the processor, other parts of the integrated circuit may be tested simultaneously with the testing of the cryptographic implementation. The processor loads in a single set of predetermined test vectors and then signals the state machine to start the testing of all the algorithms contained in the module. The output of each algorithm is used as the input of the next algorithm.

Abstract: A method of securely testing a cryptographic device need not be carried out in a secure testing facility by cleared personnel. First, a test cycle total count number is provided. Then, for each of a plurality of test cycles, the number being determined from the test cycle total count number, an input data signal is provided to the cryptographic device. The input data signal is encrypted to determine an encrypted signal, and the encrypted signal is then decrypted to determine a decrypted signal. Finally, the input data signal is compared to the decrypted signal. A cryptographic device includes receiving circuitry for receiving the input data signal and encryption circuitry that encrypts the input data signal to determine the encrypted signal. Decryption circuitry decrypts the encrypted signal to determine a decrypted signal, and comparing circuitry compares the input data signal to the decrypted signal.