Abstract: An integrated circuit sense amplifier includes a pair of complementary inputs for receiving a pair of complementary data signals which are input to a CMOS flip-flop having its output nodes connected to a logic low through a first transistor and its high side connected to a logic high through a second transistor. The first transistor is on when data signals are not being sensed, holding the nodes in a no-current, logic low state. The first transistor turns off and the second transistor turns on just prior to the arrival of a signal, precharging the nodes to an intermediate voltage, permitting the flip-flop to latch more quickly to a full-logic output when the signal arrives. A preamp may be interposed between the complementary inputs and the latch. The preamp inputs and outputs are precharged to voltage levels near or between their anticipated final levels, so that they reach their final levels quickly when the data signal arrives.

Abstract: A combined logic circuit includes an inverter and a logic gate that share a common first logic signal. The inverter has an input for receiving the first logic signal and an output for providing an inverted first logic signal. The logic gate has a first input for receiving the first logic signal and two or more secondary inputs for receiving secondary logic signals. The logic gate also includes first and second power supply nodes. The first power supply node receives the inverted first logic signal, thus actively controlling the logic function of the gate as well as eliminating a separate inverting transistor, while the second power supply node normally receives a power supply voltage. The output of the logic gate provides a predetermined logic function of the first and secondary logic signals that is equivalent to the prior art circuit. The combined logic inversion and predetermined logic function are accomplished with one less transistor than prior art circuits.

Abstract: A programmable logic array includes a dynamic AND plane, and an OR plane using clocked load devices. The high precharge voltage state in the AND plane places the logic lines in the OR plane in a low voltage state during precharge. The OR logic lines may then be pulled to a high level during the decode operation. A single clock having a delay path may be used to control the precharge and decode operations of the PLA.