Patents by Inventor Thomas H. Shilling
Thomas H. Shilling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8228679Abstract: In the present electronic structure, a substrate is provided in the form of a circuit board. First and second electronic devices are positioned on opposite sides of the circuit board, each having a plurality of contacts connected to the circuit board. Each of the contacts of the first device is connected to a contact of the second device by a connector though the circuit board. At least one of the contacts of the first device is connected to the contact of the second device which is most adjacent to that contact of the first device across the circuit board.Type: GrantFiled: April 2, 2008Date of Patent: July 24, 2012Assignee: Spansion LLCInventors: Thomas H. Shilling, Todd Snider, Melissa Grupen-Shemansky
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Patent number: 8133799Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.Type: GrantFiled: March 7, 2011Date of Patent: March 13, 2012Assignee: Agere Systems Inc.Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
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Publication number: 20110250742Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.Type: ApplicationFiled: March 7, 2011Publication date: October 13, 2011Applicant: AGERE SYSTEMS INC.Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
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Patent number: 7982307Abstract: An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.Type: GrantFiled: November 22, 2006Date of Patent: July 19, 2011Assignee: Agere Systems Inc.Inventors: Ahmed Amin, David L. Crouthamel, John W. Osenbach, Thomas H. Shilling, Brian T. Vaccaro
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Patent number: 7923347Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.Type: GrantFiled: August 24, 2009Date of Patent: April 12, 2011Assignee: Agere Systems, Inc.Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
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Publication number: 20090311853Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.Type: ApplicationFiled: August 24, 2009Publication date: December 17, 2009Applicant: Agere Systems Inc.Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
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Publication number: 20090250255Abstract: In the present electronic structure, a substrate is provided in the form of a circuit board. First and second electronic devices are positioned on opposite sides of the circuit board, each having a plurality of contacts connected to the circuit board. Each of the contacts of the first device is connected to a contact of the second device by a connector though the circuit board. At least one of the contacts of the first device is connected to the contact of the second device which is most adjacent to that contact of the first device across the circuit board.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: Thomas H. Shilling, Todd Snider, Melissa Grupen-Shemansky
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Patent number: 7598602Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.Type: GrantFiled: June 27, 2008Date of Patent: October 6, 2009Assignee: Agere Systems Inc.Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
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Publication number: 20080258275Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.Type: ApplicationFiled: June 27, 2008Publication date: October 23, 2008Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
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Patent number: 7433192Abstract: An electronic module has a non-conducting substrate having at least one opening and a die/carrier assembly mounted within the opening in the substrate. The assembly has a conducting carrier and one or more integrated circuit (IC) dies mounted to the carrier. The invention may be implemented as an electronic system comprising a circuit board (CB) and at least one such electronic module mounted to the CB.Type: GrantFiled: February 10, 2005Date of Patent: October 7, 2008Assignee: Agere Systems Inc.Inventors: Timothy B. Bambridge, Juan A. Herbsommer, Osvaldo Lopez, Joel M. Lott, Hugo F. Safar, Thomas H. Shilling
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Patent number: 7408246Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.Type: GrantFiled: March 31, 2005Date of Patent: August 5, 2008Assignee: Agere Systems, Inc.Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
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Publication number: 20080116567Abstract: An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.Type: ApplicationFiled: November 22, 2006Publication date: May 22, 2008Inventors: Ahmed Amin, David L. Crouthamel, John W. Osenbach, Thomas H. Shilling, Brian T. Vaccaro