Abstract: Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.

Abstract: Method for producing a macroporous silicon substrate suitable as a carrier for microelectronic components. Blind holes are produced from a front surface of the substrate. An insulator layer is produced on the front and rear surfaces of the substrate. Selective isotropic etching is performed from the rear surface with uncovering of blind hole ends produced such that respective blind hole walls formed by the insulator layer project from the substrate on the rear surface and are defined in this region only by the insulator layer forming the respective blind hole wall. A further insulator layer is then produced on the surfaces of the substrate. A plurality of the blind holes are then filled with a metal or a metal alloy by introducing the substrate into a melt thereof under pressure in a process chamber containing the melt. The melt is then asymmetrically cooled in the blind holes from the front surface, so that the metal or the alloy contracts toward and lies on a plane with the rear surface of the substrate.

Abstract: Device having a flat macroporous support material made of silicon and having surfaces, a plurality of pores each having a diameter in a range of from 500 nm to 100 ?m distributed over at least one surface region of the support material and extending from one surface through to the opposite surface of the support material, at least one region having one or more pores with SiO2 pore walls, and a frame of walls with a silicon core surrounding the at least one region and arranged essentially parallel to longitudinal axes of the pores and open towards the surfaces, wherein the silicon core merges into silicon dioxide over a cross section towards an outer side of the walls forming the frame.

Abstract: Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.

Abstract: A method for carrying out an amplification of nucleic acids in pores of a two-dimensionally designed macroporous support material according to one embodiment includes the step of providing a predetermined part of a reaction mixture necessary for the amplification of a nucleic acid in pores of the support material. A device for carrying out the amplification of nucleic acids according to one embodiment includes a two-dimensionally designed macroporous support material having a multiplicity of pores, wherein a predetermined part of a reaction mixture for carrying out an amplification of nucleic acids is provided in the pores.

Abstract: A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.

Abstract: The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.

Abstract: Device having a flat macroporous support material made of silicon and having surfaces, a plurality of pores each having a diameter in a range of from 500 nm to 100 ?m distributed over at least one surface region of the support material and extending from one surface through to the opposite surface of the support material, at least one region having one or more pores with SiO2 pore walls, and a frame of walls with a silicon core surrounding the at least one region and arranged essentially parallel to longitudinal axes of the pores and open towards the surfaces, wherein the silicon core merges into silicon dioxide over a cross section towards an outer side of the walls forming the frame.

Abstract: The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

Abstract: Device having a two-dimensionally formed support material which has, spread across at least one surface area, a plurality of pores which stretch throughout from one surface of the support material to the opposite surface, wherein the pores are bound in each case by a pore boundary area of pore walls formed in the support material along particular longitudinal axes of the pores, and at least part of the pore walls have at least in some sections a layered structure containing a first layer forming the pore boundary area and a second layer adjacent to the first layer and spaced apart from the pore boundary area, and wherein the refractive index nwaveguide of the first layer is greater than the refractive index n2 of the second layer.

Abstract: In a method for producing ferroelectric strontium bismuth tantalate having the composition SrxBiyTa2O9 (SBT) or SrxBiy(Ta, Nb)2O9 (SBTN), the element strontium, which is normally present in an amount y=2, is provided in excess in a range from 2.1≦y≦3.0. This makes it possible to carry out the heat treatment step for converting the deposited material into the ferroelectric phase at a temperature T1, which is lower than 700° C. In addition, the strontium content x can be reduced from a nominal value of 1 to 0.7.

Abstract: A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

Abstract: An apparatus, in which at least one pipette in the form of a through-hole with a predetermined diameter is formed in a substrate, with a rim of the through-hole projecting by a predetermined amount from an adjacent surface of the substrate.

Abstract: The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.

Abstract: The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

Abstract: The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.

Abstract: A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.

Abstract: A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region the includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

Abstract: In a method for producing ferroelectric strontium bismuth tantalate having the composition SrxBiyTa2O9 (SBT) or SrxBiy(Ta, Nb)2O9 (SBTN), the element strontium, which is normally present in an amount y=2, is provided in excess in a range from 2.1≦y≦3.0. This makes it possible to carry out the heat treatment step for converting the deposited material into the ferroelectric phase at a temperature T1, which is lower than 700° C. In addition, the strontium content x can be reduced from a nominal value of 1 to 0.7.