Abstract: Methods, systems, and devices for data scrambling for repeat operations are described. A first device may communicate a data set to a second device as a first set of bits. The first device may use a first scrambling code to scramble the first set of bits and the second device may use a first descrambling code to descramble the first set of bits. Upon determining that the first set of bits was received by the second device with an error, the first device may communicate the data set to the second device as a second set of bits. The first device may use a second scrambling code to scramble the second set of bits and the second device may use a second descrambling code to descramble the second set of bits.

Abstract: Methods, systems, and devices for command clock structure are described. A memory device may receive a command to determine a relationship (e.g., a phase relationship) between an external clock and an internally generated clock. In some examples, the memory device may execute the command and may report (e.g., to a host device) whether the command is successfully or unsuccessfully executed. The memory device may report the successful or unsuccessful execution of the command by driving one or more pins to a first value or a second value.

Abstract: Methods, systems, and devices for indicating data corruption are described. A memory system may be configured to identify and store corrupted data received from a host system without storing metadata. As part of transmitting a bulk transmission, the host system may transmit first data to be stored at an address of the memory system, and a first indication identifying that the first data is corrupted. The memory system may generate second data with a pattern of bits indicating that data stored at the address of the memory system is corrupted. The memory system may store the second data to the address, and later retrieve the second data in response to receiving a read command from the host system. Then, the memory system may generate a second indication identifying that the second data is corrupted, and transmit the second data and the second indication to the host system.

Abstract: Methods, systems, and devices for voltage overshoot mitigation at a device are described. The device may include a first driver circuit configured to generate data symbols on a transmission line and may include a second driver circuit configured to pre-emphasize the data symbols on the transmission line. The device may include a first inductor and a second inductor in series with the transmission line. A conductive line may couple the second driver circuit with a node, of the transmission line, that is between the first inductor and the second inductor.

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A first set of parameters associated with operating an interface between a host system and a memory system may be determined based on a first training operation, where an indication of the first set of parameters and a first temperature associated with the first training operation may be stored. A second set of parameters associated with operating the interface may be determined based on a second training operation, where an indication of the second set of parameters and a second temperature associated with the second training operation may be stored. At a third temperature, a third set of parameters may be configured for operation of the interface based on the stored sets of parameters, and communications over the interface may be performed in accordance with the third set of parameters.

Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.

Abstract: Methods, systems, and devices for reference voltage verification at a memory system are described. The memory system may receive a first signal that indicates to test a voltage source of a set of voltage sources corresponding to a data line of a channel of a memory system and couple the voltage source of the set with an analog-to-digital (ADC) converter to form a conductive path based on receiving the first signal. Further, the memory system may generate, using the ADC, a signal that indicates a value of a reference voltage output from the voltage source based on the conductive path.

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

Abstract: Methods, systems, and devices for command clock structure are described. A memory device may receive a command to determine a relationship (e.g., a phase relationship) between an external clock and an internally generated clock. In some examples, the memory device may execute the command and may report (e.g., to a host device) whether the command is successfully or unsuccessfully executed. The memory device may report the successful or unsuccessful execution of the command by driving one or more pins to a first value or a second value.

Abstract: Methods, systems, and devices for multi-voltage operation for driving a multi-mode channel are described. A transmitting device and a receiving device may be coupled via a channel, and the channel may support multiple modes such as a terminated mode and an unterminated mode. A driver may be coupled with the channel, and a voltage supply for the driver may be adjusted based on the mode of the channel, such as based on whether the channel is terminated or unterminated. Adjusting the voltage supply may result in similar or otherwise desirable voltage levels on the channel for each mode of the channel.

Abstract: Methods, systems, and devices for error control for fuse arrays are described. The described techniques may enable a memory system to perform error control on a fuse block. The fuse block may include one or more fuses that store error control information that is generated based on the control information stored in the corresponding fuse block. The memory system may therefore use the error control information to determine whether the fuse block contains an error and to correct one or more errors contained in the fuse block. In some examples, the memory system may output an error flag or update an error log when an error is detected. In some examples, each fuse block may include multiple sets of error control fuses, and a fuse selector may determine which set of error control fuses to use for error control of the fuse block.

Abstract: Methods, systems, and devices for data path protection in memory systems are described. A memory system may calculate a data path protection (DPP) parity bit to ensure data transferred between the memory system and a host system is accurate. For example, the memory system may perform, as part of an error correction code (ECC) operation, multiple first logical operations on data bits to generate ECC parity bits. In response to generating the ECC parity bits, the memory system may perform, as part of a data path parity operation, multiple second logical operations on the ECC parity bits to generate an intermediate parity bit, where the memory system may perform a third logical operation between a single error correction bit and the intermediate parity bit to generate a DPP parity bit. In such examples, the memory system may output the DPP parity bit to the host system.

Abstract: Methods, systems, and devices for data path protection with parity information are described. A data path protection scheme for a data path within a memory system may include conveying poison information and parity information via the data path. A data encoder of the data path may convert data between first and second modulation schemes using codewords. The data encoder may repurpose a reserved, unused, or unassigned codeword to indicate the poison information. For example, the data encoder may output the reserved codeword to indicate that corresponding data is poisoned. The data encoder may output the reserved codeword in place of a portion of the poisoned data. An encoder previously used to encode the poison information may be used to convey the parity information in the data path, and may output a fourth codeword representative of the parity information to provide data protection for the data path.

Abstract: Methods, systems, and devices for multiple fuse comparison for early failure check are described. The method may include a memory system receiving signaling that indicates a first resistance level associated with one or more first fuses of a first set of fuses and receiving signaling that indicates a second resistance level associated with one or more second fuses of a second set of fuses that stores redundant data with respect to the first set of fuses. Further, the method may include generating an error flag associated with the fuse array based on a comparison of the first resistance level and the second resistance level.

Abstract: The present relates to a method for operating a vehicle brake system which comprises a vehicle brake having a brake piston, an electrohydraulic service brake device, and an electromotive parking brake device having a spindle drive driven by an electric motor, wherein the electrohydraulic service brake device and/or the electromotive parking brake device act on the brake piston. The method determines an additional brake fluid volume to be delivered by the electrohydraulic service brake device in order to ensure a target clamping force (Fz-Soll) for a brake pad of the parking brake on application of the parking brake device.

Abstract: Methods, systems, and devices for asynchronous multi-level signal sampling are described. A system may generate a first clock signal by delaying the master clock signal by a first duration that is based on a first propagation delay associated with a first amplifier for a data signal. The system may generate a second clock signal by delaying the master clock signal by a second duration that is based on a second propagation delay associated with a second amplifier for the data signal. The system may sample, by a first sampling circuit based on the first clock signal, a first amplified data signal outputted by the first amplifier. And the system may sample, by a second sampling circuit based on the second clock signal, a second amplified data signal outputted by the second amplifier.

Abstract: Methods, systems, and devices for voltage overshoot mitigation at a device are described. The device may include a first driver circuit configured to generate data symbols on a transmission line and may include a second driver circuit configured to pre-emphasize the data symbols on the transmission line. The device may include a first inductor and a second inductor in series with the transmission line. A conductive line may couple the second driver circuit with a node, of the transmission line, that is between the first inductor and the second inductor.

Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.

Abstract: Methods, systems, and devices for multi-voltage operation for driving a multi-mode channel are described. A transmitting device and a receiving device may be coupled via a channel, and the channel may support multiple modes such as a terminated mode and an unterminated mode. A driver may be coupled with the channel, and a voltage supply for the driver may be adjusted based on the mode of the channel, such as based on whether the channel is terminated or unterminated. Adjusting the voltage supply may result in similar or otherwise desirable voltage levels on the channel for each mode of the channel.

Abstract: Methods, systems, and devices for systems and techniques for error testing are described. As part of a first write operation, a memory system may write data and associated error correction code (ECC) bits to a memory array. In accordance with a first portion of a test, the memory system may store a copy of the ECC bits to a register of the memory system. As part of a second write operation, the memory system may write an error vector to the memory array. In accordance with a second portion of the test, the memory system may store the previously-stored ECC bits from the register to the memory array. The memory system may subsequently access the error vector and the ECC bits from the memory array to support verification of error correction and detection performance of the memory system.