Abstract: An internal combustion engine with a crankcase ventilation system is provided, which, comprises a crankcase, an air intake line. The air intake line comprises a throttle valve and an air filter, and a crankcase ventilation line for venting the crankcase and a crankcase aeration line for flushing the crankcase. The crankcase ventilation line is arranged at a first junction downstream of the air filter at the air intake line. The crankcase aeration line, a sensor unit is arranged downstream of a first flow control device and upstream of a first backflow prevention device. The first junction is arranged downstream at a distance from a crankcase aeration line connection at the air intake line so that a malfunction of the crankcase ventilation system can be detected by the sensor unit.

Abstract: Methods, systems, and devices for receiver decision feedback equalization calibration are described. A memory system may support implementing respective decision feedback equalization (DFE) values at respective receivers using interpolation logic. For example, a calibration circuit may generate and store a quantity of candidate voltage values corresponding to the application of different DFE values at the receivers. The memory system may use the interpolation logic to generate (e.g., interpolate, generate) respective voltage values corresponding to a DFE value for application at a respective receiver based on the stored candidate voltage values. The interpolation logic may output the voltage values via a serial bus to each receiver, and each receiver may apply, to respectively received data, a DFE value corresponding to a respectively received voltage value.

Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

Abstract: Methods, systems, and devices for memory operations that support configuring a channel, such as a command/address (C/A) channel, are described. A configuration of a C/A channel may be dynamically adapted based on power saving considerations, control information execution latency, or both. Configuring a C/A channel may include determining a quantity of pins, or a quantity of cycles, both for communicating control information over the C/A channel. The quantity of pins may be determined based on previous control information transmissions, characteristics of a memory device, or predicted control information transmissions, or any combination thereof in some cases. The determined quantity of pins, quantity of cycles, or both may be explicitly or implicitly indicated to other devices (e.g., that use the C/A channel).

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds are configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device configures a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device tracks or counts errors in the data and determine whether the threshold has been satisfied. The memory device transmits (e.g., to the host device) an indication whether the threshold has been satisfied, and the system performs functions to correct the errors and/or prevent further errors. The memory device also identifies errors in received commands or identifies errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

Abstract: Methods, systems, and devices for indicating data corruption are described. A memory system may be configured to identify and store corrupted data received from a host system without storing metadata. As part of transmitting a bulk transmission, the host system may transmit first data to be stored at an address of the memory system, and a first indication identifying that the first data is corrupted. The memory system may generate second data with a pattern of bits indicating that data stored at the address of the memory system is corrupted. The memory system may store the second data to the address, and later retrieve the second data in response to receiving a read command from the host system. Then, the memory system may generate a second indication identifying that the second data is corrupted, and transmit the second data and the second indication to the host system.

Abstract: Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

Abstract: Methods, systems, and devices for bit inversion techniques for memory system repair indications are described. A memory system may store an address of a failed access line or an inversion of the address based on a quantity of bits having a first bit value. For example, if an address has a quantity of ‘1’s that is greater than a threshold, the memory system may store an inversion of the address by inverting the address and setting one-time programmable (OTP) elements to indicate the inverted ‘1’s. The memory system may also store an additional inversion bit to indicate the inversion of the address. For reading the OTP elements, the memory system may interpret an address as inverted or non-inverted based on the inversion bit. The memory system may also indicate one or more steps of a repair process to a host system to facilitate communication during repair procedures.

Abstract: Methods, systems, and devices for maintaining integrity of configuration data for memory devices are described. A memory system may implement an error control component configured to detect errors in configuration data stored to one or more mode registers. The error control component may be configured to generate error control information, including one or more parity bits or a checksum, associated with the configuration data. The memory system or a host system coupled with the memory system may be configured to detect errors in the configuration data based on the error control information. Based on detecting the errors, the memory system may enter a safe mode, in which the memory system refrains from performing access operations until the configuration data is rewritten to the one or more mode registers.

Abstract: Methods, systems, and devices for metadata transfer using unassigned codes of an encoder are described. The method may include inputting data and metadata associated with the data into an encoder. The data may include a first set of codewords modulated using a first modulation scheme including symbols that each represent one bit of digital information. Further, the method may include generating, using the encoder, a first subset of a second set of codewords representative of the data and a second subset of the second set of codewords representative of the metadata. The second set of codewords may be modulated using a second modulation scheme including symbols that each represent more than one bit of digital information. Further, the method may include transmitting the data and the metadata using the second set of codewords.

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A first set of parameters associated with operating an interface between a host system and a memory system may be determined based on a first training operation, where an indication of the first set of parameters and a first temperature associated with the first training operation may be stored. A second set of parameters associated with operating the interface may be determined based on a second training operation, where an indication of the second set of parameters and a second temperature associated with the second training operation may be stored. At a third temperature, a third set of parameters may be configured for operation of the interface based on the stored sets of parameters, and communications over the interface may be performed in accordance with the third set of parameters.

Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Abstract: Methods, systems, and devices for techniques for data path address protection are described. As part of a write operation, the memory system may receive data associated with the write operation and an address for the data from a host system. The memory system may generate a first codeword using the address and may store both the first codeword and the data at the address. In some examples, the memory system may generate a second codeword using the data and the first codeword and store the second codeword along with the data and the first codeword. As part of a subsequent read operation for the data, the memory system may receive the address from the host system and retrieve the stored data and first codeword. The memory system may generate a third codeword using the address associated with the read operation and may compare the third codeword with the first codeword.

Abstract: Methods, systems, and devices for temperature-based memory management are described. A system may include a memory device and a host device. The host device may identify a temperature (e.g., of the memory device). The host device may determine a value for a parameter for operating the memory device—such as a timing, voltage, or frequency parameter—based on the temperature of the memory device. The host device may transmit signaling to the memory device or another component of the system based on the value of the parameter. In some cases, the host device may determine the temperature of the memory device based on an indication (e.g., provided by the memory device). In some cases, the host device may determine the temperature of the memory device based on a temperature of the host device or a temperature of another component of the system.