Abstract: A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only.

Abstract: A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate array arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only.

Abstract: A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only.

Abstract: A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate array arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only.

Abstract: A III-nitride power semiconductor device that includes a two dimensional electron gas having a reduced charge region under the gate thereof.

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element.

Abstract: A low contact resistance ohmic contact for a III-Nitride or compound semiconductor wafer or die consists of 4 layers of Ti, AlSi, Ti and TiW. The AlSi has about 1% Si. The layers are sequentially deposited as by sputtering, are patterned and plasma etched and then annealed in a rapid thermal anneal process. The use of AlSi in place of pure Al reduces contact resistance by about 15% to 30%.

Abstract: A III-nitride power semiconductor device that includes a two dimensional electron gas having a reduced charge region under the gate thereof.

Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

Abstract: A III-nitride power semiconductor device that includes a two dimensional electron gas having a low field region under the gate thereof.

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: A III-nitride power semiconductor device that includes a two dimensional electron gas having a low field region under the gate thereof.

Abstract: A low contact resistance ohmic contact for a III-Nitride or compound semiconductor wafer or die consists of 4 layers of Ti, AlSi, Ti and TiW. The AlSi has about 1% Si. The layers are sequentially deposited as by sputtering, are patterned and plasma etched and then annealed in a rapid thermal anneal process. The use of AlSi in place of pure Al reduces contact resistance by about 15% to 30%.

Abstract: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element.

Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

Abstract: A vertical MOSFET has a substrate of a first conductivity type. A channel region of a second conductivity type is diffused into the substrate. A gate is disposed at least partially over the channel region. A source region of a second conductivity type is disposed proximate to the gate and adjacent to the channel region. The channel region includes a depletion implant area proximate to the gate. The depletion implant species is of the second conductivity type to reduce the concentration of the first conductivity type in the channel region without increasing the conductivity in the drain/drift region.