Patents by Inventor Thomas Herrick

Thomas Herrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11489814
    Abstract: Methods, systems, and computer-readable media for customized domain name resolution for virtual private clouds are disclosed. A domain name system (DNS) resolution service receives a DNS request from a computing resource associated with a virtual private cloud (VPC) in a cloud provider network. The service determines that the VPC is associated with one or more firewall rules. Responsive to determining that the VPC is associated with the firewall rule(s), the service determines whether the DNS request is allowed or blocked according to the one or more firewall rules. If the DNS request is allowed, the service resolves the DNS request using a DNS server and returns a response to the computing resource. If the DNS request is blocked, the service does not resolve the DNS request.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: November 1, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Matthew Engskow, Kiran Thunga, Vikram Saurabh, Yu Wang, Huida Tao, Rishi Goel, Kevis Tsao, Abhay Raina, Alexander Thomas Herrick, Jeffrey J Damick, Hemakshi Sharma
  • Patent number: 6566264
    Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: May 20, 2003
    Assignee: Motorola, Inc.
    Inventors: Nigel Graeme Cave, Matthew Thomas Herrick, Terry Grant Sparks
  • Patent number: 6372665
    Abstract: In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: April 16, 2002
    Assignee: Motorola Inc.
    Inventors: Joy Kimi Watanabe, Matthew Thomas Herrick, Terry Grant Sparks, Nigel Graeme Cave
  • Patent number: 6232235
    Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: May 15, 2001
    Assignee: Motorola, Inc.
    Inventors: Nigel Graeme Cave, Matthew Thomas Herrick, Terry Grant Sparks
  • Patent number: 6218302
    Abstract: An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: April 17, 2001
    Assignee: Motorola Inc.
    Inventors: Gregor Braeckelmann, Ramnath Venkatraman, Matthew Thomas Herrick, Cindy R. Simpson, Robert W. Fiordalice, Dean J. Denning, Ajay Jain, Cristiano Capasso
  • Patent number: 6127258
    Abstract: In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: October 3, 2000
    Assignee: Motorola Inc.
    Inventors: Joy Kimi Watanabe, Matthew Thomas Herrick, Terry Grant Sparks, Nigel Graeme Cave
  • Patent number: D343942
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: February 1, 1994
    Inventors: Thomas Herrick, Walter Dombrowski
  • Patent number: D353992
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: January 3, 1995
    Assignee: H & D Designs, Inc.
    Inventors: Walter Dombrowski, Thomas Herrick
  • Patent number: D986727
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: May 23, 2023
    Assignee: ASHLEY FURNITURE INDUSTRIES, LLC
    Inventors: Jeremy Thomas Herrick, Karl Joseph Fegi
  • Patent number: D1013493
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: February 6, 2024
    Assignee: Ashley Furniture Industries, LLC
    Inventors: Jeremy Thomas Herrick, Karl Joseph Fegi