Patents by Inventor Thomas HISCOCK

Thomas HISCOCK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907682
    Abstract: This device comprises a fast sampler comprising: a truncated table associating with truncated random numbers rmsb coded on Nmsb bits, the only sample k for which, whatever the number rlsb belonging to the interval [0; 2Nr?Nmsb?1], the following condition is met: F(k?1)<(rmsb, rlsb)?F(k), where: (rmsb, rlsb) is the binary number coded on Nr bits and the Nmsb most significant bits of which are equal to the truncated random number rmsb and the (Nr?Nmsb) least significant bits of which are equal to the number rlsb, Nmsb is an integer number lower than Nr, a module for searching for a received truncated random number rmsb in the truncated table, and able to transmit the sample k, associated, by the truncated table, with the received truncated random number rmsb, by way of random number drawn according to the probability distribution ?.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 20, 2024
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Thomas Hiscock
  • Publication number: 20230176982
    Abstract: A management system for managing a cache memory including a randomization module configured for generating a random value for each process of accessing the cache memory, and for transforming addresses of the cache memory with said random value into randomized addresses, a history table configured to store therein on each line an identification pair associating a random value corresponding to an access process, with an identifier of the corresponding access process, so forming identification pairs that are operative to dynamically partition the cache memory while registering the access to the cache memory, and a state machine configured to manage each process of accessing the cache memory according to the identification pairs stored in the history table.
    Type: Application
    Filed: November 14, 2022
    Publication date: June 8, 2023
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Mustapha EL MAJIHI, Amine JAAMOUM, Billal IGHILAHRIZ, Thomas HISCOCK
  • Patent number: 11651086
    Abstract: A method for executing a computer program, wherein when a microprocessor writes a block of No bytes of a datum of a block of cleartext data stored in an unencrypted memory, a security module switches a validity indicator associated with this block of No bytes to an active state wherein it indicates that this block of bytes is valid, and each time a block of No bytes of a datum of the block of cleartext data is loaded by the microprocessor from the unencrypted memory, the hardware security module verifies whether the validity indicator associated with this block of No bytes is in its active state and, if such is the case, processing, by the microprocessor, of this block of No bytes is permitted, and, if such is not the case, processing, by the microprocessor, of this block of No bytes is forbidden.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: May 16, 2023
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier Savry, Thomas Hiscock
  • Publication number: 20220292182
    Abstract: A method for the execution of a binary code defining a data structure including a particular field to be read using a pointer, this method including writing, to the main memory, the value of the particular field associated with a first identifier of a pointer that points directly to this particular field, this identifier being determined from an identifier of the particular field that differs for all of the fields of the data structure that are adjacent to the particular field, and then constructing a pointer that points directly to this particular field, this construction including determining an identifier of this constructed pointer, and then checking that the identifier constructed in step b) corresponds to the identifier associated with this particular field in step a), and when these pointer identifiers do not match, triggering the signaling of an execution fault.
    Type: Application
    Filed: February 14, 2022
    Publication date: September 15, 2022
    Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier SAVRY, Thomas HISCOCK
  • Publication number: 20220294634
    Abstract: A method for executing a computer program includes incorporating, into metadata of a block containing a line of code to be accessed using a pointer, a first pointer identifier associated with the line of code to be accessed, then obtaining a pointer including a first range of bits containing the address of the line of code to be accessed, and a different second range of bits containing a second pointer identifier, then verifying that the second pointer identifier contained in the obtained pointer corresponds to the first pointer identifier associated with the line of code to be accessed and contained in the metadata of the loaded block, and when the first and second pointer identifiers do not correspond, then the security module triggers signaling of an execution fault.
    Type: Application
    Filed: February 14, 2022
    Publication date: September 15, 2022
    Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier Savry, Thomas Hiscock
  • Patent number: 11157659
    Abstract: A method for executing a polymorphic machine code, wherein: for each branching address at which a base block of a flow of generated instructions starts, the microprocessor automatically adds, in the generated flow of instructions, a renewal instruction suitable, when it is executed, for triggering the renewal of an initialization vector of a module for decryption by flow with a specific value associated with this branching address, then a flow encryption module encrypts the flow of instructions as it is generated and, during this encryption, each base block is encrypted using a specific value associated with the branching address at which it starts. Only the instruction flow encrypted in this way is recorded in the main memory. During execution of the encrypted instruction flow, the added renewal instructions are executed as they are encountered.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 26, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Damien Courousse, Thomas Hiscock, Olivier Savry
  • Patent number: 11144470
    Abstract: Method for managing a cache memory comprising: the transformation of a received set address in order to find a word in the cache memory, into a transformed set address by means of a bijective transformation function, the selection of one or more line tags stored in the cache memory at the transformed set address. in which: the transformation function is parameterized by a parameter q such that the transformed set address obtained depends both on the received set address and on the value of this parameter q, and for all the non-zero values of the parameter q, the transformation function permutes at least 50% of the set addresses, and during the same execution of the process, a new value of the parameter q is repeatedly generated for modifying the transformation function.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 12, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Thomas Hiscock, Mustapha El Majihi, Olivier Savry
  • Publication number: 20210216283
    Abstract: This device comprises a fast sampler comprising: a truncated table associating with truncated random numbers rmsb coded on Nmsb bits, the only sample k for which, whatever the number rlsb belonging to the interval [0; 2Nr?Nmsb?1], the following condition is met: F(k?1)<(rmsb, rlsb)?F(k), where: (rmsb, rlsb) is the binary number coded on Nr bits and the Nmsb most significant bits of which are equal to the truncated random number rmsb and the (Nr-Nmsb) least significant bits of which are equal to the number rlsb, Nmsb is an integer number lower than Nr, a module for searching for a received truncated random number rmsb in the truncated table, and able to transmit the sample k, associated, by the truncated table, with the received truncated random number rmsb, by way of random number drawn according to the probability distribution ?.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 15, 2021
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Thomas HISCOCK
  • Publication number: 20210173946
    Abstract: A method for executing a computer program, wherein when a microprocessor writes a block of No bytes of a datum of a block of cleartext data stored in an unencrypted memory, a security module switches a validity indicator associated with this block of No bytes to an active state wherein it indicates that this block of bytes is valid, and each time a block of No bytes of a datum of the block of cleartext data is loaded by the microprocessor from the unencrypted memory, the hardware security module verifies whether the validity indicator associated with this block of No bytes is in its active state and, if such is the case, processing, by the microprocessor, of this block of No bytes is permitted, and, if such is not the case, processing, by the microprocessor, of this block of No bytes is forbidden.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 10, 2021
    Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier SAVRY, Thomas HISCOCK
  • Patent number: 11003593
    Abstract: A method for managing a cache memory, including executing first and second processes, when the second process modifies the state of the cache memory, updating the value of an indicator associated with this second process, and comparing the value of this indicator to a predefined threshold and, when this predefined threshold is exceeded, detecting an abnormal use of the cache memory by the second process, in response to this detection, modifying pre-recorded relationships in order to associate with the identifier of the second process a value of a parameter q different from the value of the parameter q associated with the first process so that, after this modification, when the received address of a word to be read is the same for the first and second processes, then the set addresses used to read this word from the cache memory are different.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 11, 2021
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Thomas Hiscock, Mustapha El Majihi, Olivier Savry
  • Publication number: 20200257637
    Abstract: A method for managing a cache memory, including executing first and second processes, when the second process modifies the state of the cache memory, updating the value of an indicator associated with this second process, and comparing the value of this indicator to a predefined threshold and, when this predefined threshold is exceeded, detecting an abnormal use of the cache memory by the second process, in response to this detection, modifying pre-recorded relationships in order to associate with the identifier of the second process a value of a parameter q different from the value of the parameter q associated with the first process so that, after this modification, when the received address of a word to be read is the same for the first and second processes, then the set addresses used to read this word from the cache memory are different.
    Type: Application
    Filed: January 16, 2020
    Publication date: August 13, 2020
    Applicant: Commissariat a I'Energie Atomique et aux Energies Alternatives
    Inventors: Thomas HISCOCK, Mustapha EL MAJIHI, Olivier SAVRY
  • Patent number: 10740068
    Abstract: A modular reduction device particularly for cryptography on elliptical curves. The device includes a Barrett modular reduction circuit and a cache memory in which the results of some precalculations are carried out. When the result is not present in the cache memory, a binary division circuit makes the precalculation and stores the result in the cache memory.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 11, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Thomas Hiscock
  • Publication number: 20200192813
    Abstract: Method for managing a cache memory comprising: the transformation of a received set address in order to find a word in the cache memory, into a transformed set address by means of a bijective transformation function, the selection of one or more line tags stored in the cache memory at the transformed set address. in which: the transformation function is parameterized by a parameter q such that the transformed set address obtained depends both on the received set address and on the value of this parameter q, and for all the non-zero values of the parameter q, the transformation function permutes at least 50% of the set addresses, and during the same execution of the process, a new value of the parameter q is repeatedly generated for modifying the transformation function.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 18, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Thomas HISCOCK, Mustapha EL MAJIHI, Olivier SAVRY
  • Publication number: 20200089919
    Abstract: A method for executing a polymorphic machine code, wherein: for each branching address at which a base block of a flow of generated instructions starts, the microprocessor automatically adds, in the generated flow of instructions, a renewal instruction suitable, when it is executed, for triggering the renewal of an initialization vector of a module for decryption by flow with a specific value associated with this branching address, then a flow encryption module encrypts the flow of instructions as it is generated and, during this encryption, each base block is encrypted using a specific value associated with the branching address at which it starts. Only the instruction flow encrypted in this way is recorded in the main memory. During execution of the encrypted instruction flow, the added renewal instructions are executed as they are encountered.
    Type: Application
    Filed: December 14, 2017
    Publication date: March 19, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Damien COUROUSSE, Thomas HISCOCK, Olivier SAVRY
  • Patent number: 10439798
    Abstract: A method of executing a program operating on data encrypted by a homomorphic encryption. Execution of a program instruction includes the homomorphic evaluation of an associated function in the ciphertext space, homomorphic masking of the result of the evaluation with a previously encrypted random sequence, decryption of the evaluation result thus masked followed by a new encryption and then homomorphic unmasking in the ciphertext space. The result of execution of the instruction does not appear in plain text at any time during execution of the instruction.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: October 8, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Savry, Thomas Hiscock
  • Patent number: 10305682
    Abstract: A method of encrypting a program instructions stream and a method of executing an instructions stream thus encrypted. Instructions are translated into binary code before being encrypted by a stream cipher method. When the program contains a conditional or unconditional branch instruction, an instruction is inserted in the program to initialize the pseudo-random sequence generator using an initialization vector, the initialization vector being used to generate the pseudo-random sequence for encryption and decryption of instructions at the branch address. Instructions can be decrypted and executed on-the-fly without needing to know their physical addresses, even in the presence of a branch.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: May 28, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Florian Pebay-Peyroula, Olivier Savry, Thomas Hiscock
  • Publication number: 20190073196
    Abstract: A modular reduction device particularly for cryptography on elliptical curves. The device includes a Barrett modular reduction circuit and a cache memory in which the results of some precalculations are carried out. When the result is not present in the cache memory, a binary division circuit makes the precalculation and stores the result in the cache memory.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 7, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Thomas HISCOCK
  • Publication number: 20170244553
    Abstract: A method of executing a program operating on data encrypted by a homomorphic encryption. Execution of a program instruction includes the homomorphic evaluation of an associated function in the ciphertext space, homomorphic masking of the result of the evaluation with a previously encrypted random sequence decryption of the evaluation result thus masked followed by a new encryption and then homomorphic unmasking in the ciphertext space. The result of execution of the instruction does not appear in plain text at any time during execution of the instruction.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 24, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier SAVRY, Thomas Hiscock
  • Publication number: 20170214523
    Abstract: A method of encrypting a program instructions stream and a method of executing an instructions stream thus encrypted. Instructions are translated into binary code before being encrypted by a stream cipher method. When the program contains a conditional or unconditional branch instruction, an instruction is inserted in the program to initialise the pseudo-random sequence generator using an initialisation vector, the initialisation vector being used to generate the pseudo-random sequence for encryption and decryption of instructions at the branch address. Instructions can be decrypted and executed on-the-fly without needing to know their physical addresses, even in the presence of a branch.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 27, 2017
    Applicant: COMMISSARIAT A L'ENERGIE A TOMIQUE ET AUX ENERGIES AL TERNATIVES
    Inventors: Florian PEBAY-PEYROULA, Olivier SAVRY, Thomas HISCOCK