Abstract: Roughly described, a method of controlling transportation of debug data on an integrated circuit chip. The chip has a shared hub and a number of peripheral circuits. Each peripheral circuit is connected to a respective debug unit, and between each debug unit and the shared hub there is an interface configured to transport data messages over each of a number of prioritized flows. In the method, still roughly described, control data for controlling the state of a debug unit is transported on a priority flow having a first priority, and debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit is transported on a flow having a second priority, the first priority being higher than the second priority.

Abstract: Roughly described, a method of sending a message from a source unit to a destination unit both forming part of a hierarchical debug architecture on a chip, the units in the hierarchy using a protocol in which each unit has an internal address which is the same base address, and in which each unit addresses other units using addresses derivable relative to that unit's internal address given positions of other units in the hierarchy, comprising: the source unit in a first level of the hierarchy sending a message comprising a destination address of the destination unit, the destination address being relative to the source unit's internal address, and an intermediate unit in a second level of the hierarchy: adding an offset to the destination address to form a rebased destination address, being relative to the intermediate unit's internal address, and routing the rebased message onto the destination unit.

Abstract: A data processing apparatus having processing circuitry and debug circuitry is debugged by operating the processing circuitry to generate data. The debug circuitry is employed to generate trace elements indicative of the operation of the processing circuitry. Trace elements are caused to be output from the data processing apparatus over a communication bus capable of connecting a plurality of devices. The communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system. The passing of the trace elements onto the communication bus is controlled using an interface unit of the debug circuitry. The interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.

Abstract: Improving start-up time of a light emitting diode (led) driver at lower input voltage is accomplished with a quick start circuit comprising a constant current source that replaces the traditional trickle charge start-up path for charging of a Vcc capacitor supplying operating voltage to an SMPS controller. Also the constant current source will only be operational during SMPS start-up, then will turn off after the SMPS is capable of producing its own regulated power supply to the Vcc terminal of the SMPS controller, thereby minimizing E2/R power losses in the SMPS.

Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit; a shared hub; and between each respective debug unit and the shared hub, a single physical interface configured to transport both configuration data and event data, wherein the interface is configured such that if an event occurs whilst the interface is transporting configuration data, the interface interrupts the transport of the configuration data in order to transport the event data.

Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Abstract: Roughly described, a method of controlling transportation of debug data on an integrated circuit chip, the integrated circuit chip comprising a shared hub and a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, wherein between each respective debug unit and the shared hub there is an interface configured to transport data messages over each of a plurality of flows, the flows being assigned priorities, the method comprising: transporting control data for controlling the state of a debug unit on a priority flow having a first priority; and transporting debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit on a flow having a second priority, wherein the first priority is higher than the second priority.

Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.

Abstract: Roughly described, a method of sending a message from a source unit to a destination unit both forming part of a hierarchical debug architecture on a chip, the units in the hierarchy using a protocol in which each unit has an internal address which is the same base address, and in which each unit addresses other units using addresses derivable relative to that unit's internal address given positions of other units in the hierarchy, comprising: the source unit in a first level of the hierarchy sending a message comprising a destination address of the destination unit, the destination address being relative to the source unit's internal address, and an intermediate unit in a second level of the hierarchy: adding an offset to the destination address to form a rebased destination address, being relative to the intermediate unit's internal address, and routing the rebased message onto the destination unit.

Abstract: Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.

Abstract: Total harmonic distortion (THD) at the AC line input of a power factor corrected (PFC) flyback switch mode power supply (SMPS) is reduced by adding additional current injection to the current programming signal of a PFC controller during the period of the line cycle where the AC input current wave shape is most flattened, i.e., around the peak portion of the AC line voltage. The input current drawn by the PFC flyback SMPS will then more closely resemble a desired sinusoidal waveform. A voltage dependent non-linear resistance is coupled in parallel with the normal current injection resistor that supplies current to the PFC flyback controller multiplier input to inject appropriate values of additional current into the PFC flyback controller based upon the AC input voltage value(s) so as to better shape the AC input current to the desired sinusoidal waveform.

Abstract: A circuit for dimming a lamp is provided. The circuit includes a triac dimmer that adjusts the voltage level of an input AC waveform based on the setting of a dimmer switch. The output of the dimmer is provided to a power supply circuit that drives the lamp based on the voltage level at the dimmer output. The power supply circuit includes a compensation circuit that compensates for loss of dimmer output signal caused by the triac when the dimmer switch is adjusted for full output. The compensation circuit is configured to engage at dimmer output voltage levels between full power supply voltage and a voltage threshold. The voltage threshold may be based on the dimmer output voltage level when the dimmer switch is set for full output. The compensation circuit essentially disengages to allow the lamp to dim when the dimmer output voltage level falls below the threshold.

Abstract: A data processing apparatus, comprising processing circuitry, which in use, generates data and debug circuitry arranged to debug operation of the processing circuitry. The processing circuitry includes bus circuitry arranged to pass data at least one of into and out of the processing apparatus over a communication bus. The debug circuitry comprises monitoring circuitry arranged to monitor the data generated, in use, by the processing circuitry and generate a stream of trace elements. An interface unit is arranged to interface, using the bus circuitry, the trace elements generated by the monitoring circuitry onto the communication bus to be output, in use, from the processing apparatus using the communication bus. The interface unit comprises a controller which is arranged to control operation of the interface unit independently of the operation of the processing circuitry.

Abstract: A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.

Abstract: A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.

Abstract: A semiconductor device has first and second semiconductor chips comprising electronic circuit elements located at an inner part of the chip and first connection terminals located on an upper surface of the inner part of the chip. One of the chips has second connection terminals located at a peripheral part of the chip. The first and second semiconductor chips are mounted one on top of the other to form the device connected together by the first connection terminals of the first and second semiconductor chips, and wherein the second connection terminals of the first semiconductor chip provide external connections to the device. The invention enables SoC resources to be increased based on the System-in-Package (SiP) approach by duplication identical chip components into a single package.

Abstract: A fluorescent lamp assembly includes a fluorescent lamp ballast capable of detecting at least one of a plurality of input signals and generating an output signal. The output signal is associated with a power level that is based on the at least one detected input signal. The fluorescent lamp assembly also includes a fluorescent lamp capable of receiving the output signal and generating light. An intensity of the light is based on the power level associated with the output signal.

Abstract: A system controls an induction motor driven by a power inverter circuit. An operational amplifier circuit is operatively connected to the power inverter circuit and operative therewith for sensing DC current and controlling acceleration and deceleration of the induction motor. The operational amplifier circuit includes a first operational amplifier operative in a motoring mode to have a positive polarity output and remain substantially at zero during a regeneration mode. A second operational amplifier circuit is operative in a regeneration mode to have a negative polarity output and remain substantially at zero in a motoring mode.

Abstract: A fluorescent lamp assembly includes a fluorescent lamp ballast capable of detecting at least one of a plurality of input signals and generating an output signal. The output signal is associated with a power level that is based on the at least one detected input signal. The fluorescent lamp assembly also includes a fluorescent lamp capable of receiving the output signal and generating light. An intensity of the light is based on the power level associated with the output signal.

Abstract: A thermally printable commercially functional cash register tape produced from a thin oriented, heat stabilized, thermoplastic film is described. This thermoplastic tape replaces the currently used paper cash register tape. It will accept printing, has sufficient machine direction stiffness and sufficiently reduced surface electrical charges to function in conventional commercial cash register printers. The thermoplastic tape is much thinner than the conventional paper tape so a roll of the plastic register tape contains about 4.7 times the paper length of a typical cash register roll.