Abstract: An exterior mirror assembly for a vehicle includes a mirror head having a mirror housing and a reflective element, which is disposed so as to be adjustable at the mirror housing. The mirror assembly includes a mirror base or mounting base and an actuator for electric inward folding. The mirror assembly includes a sealing element that seals between the mirror head and the mirror base at least when the mirror head is in a use or extended position. When the mirror head is pivoted between the use position and a folded or stowed position, the sealing element is disengaged from the mirror head or the mirror base to allow for reduced friction pivoting of the mirror head relative to the mirror base. The sealing element may be mechanically moved to disengage or may disengage responsive to an electromagnetic element. The mirror assembly may include a light/indicator module.

Abstract: An illumination unit for a vehicle component of a vehicle includes a housing and at least one light source that emits light through a light diffusion component and a light-deflecting film. The light-deflecting film is adapted to conform to an exterior contour of a vehicle component. The light-deflecting film closes the housing and has an inner side and an outer side, with the inner side closer to the light source than the outer side. The light-deflecting film has a microstructure on the outer side that deflects light emitted by the light source in a direction that differs from the angle of incidence of the emitted light at the inner side of the light-deflecting film.

Abstract: An illumination unit for a vehicle component of a vehicle includes a housing and at least one light source that emits light through a light diffusion component and a light-deflecting film. The light-deflecting film is adapted to conform to an exterior contour of a vehicle component. The light-deflecting film closes the housing and has an inner side and an outer side, with the inner side closer to the light source than the outer side. The light-deflecting film has a microstructure on the outer side that deflects light emitted by the light source in a direction that differs from the angle of incidence of the emitted light at the inner side of the light-deflecting film.

Abstract: A system, method and software is described for the advertising of real estate. Information and images for a property are made available to prospective purchasers. Users' interactions are tracked, and points are assigned for each interaction. For each property listing, the system and software identify a segment of other relevant property listings. Each property listing is compared to the listings in its segment on the basis of points to determine its relative ranking. The relative ranking is used to determine the fee charged to the seller for use of the system and software. The system and software generate and provide reports and recommendations to users.

Abstract: A computer readable medium is provided embodying instructions executable by a processor to perform a method for caching video data in a two-dimensional cache. The method includes storing the video data in the two-dimensional cache, addressing stored video data in the two-dimensional cache using a first tag for referencing video data of a first dimension, addressing the stored video data in the cache in terms of a second tag for referencing video data of a second dimension, and retrieving and outputting a portion of the stored video data from the two-dimensional cache according to one of the first tag and the second tag.

Abstract: A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes. This data cache includes a plurality of input ports for receiving the LDPC codes from some of the processing units, and a plurality of output ports for sending the LDPC codes to others of the processing units. An off-chip, external memory stores the LDPC codes and transmits the LDPC codes to and receives the LDPC codes from at least some of the processing units. A sequence processor controls the transmission of the LDPC codes between the processor units and the on-chip data cache so that the LDPC codes are processed by the processing units according to a given sequence.

Abstract: A method and apparatus, particularly suited to SIMD instruction sets, to filter streaming video information encoded under a predictive encoding algorithm specified under video encoding standards, such as MPEG 4 or H.264/AVC. The filtering operation de-blocks or removes unwanted borders in the perceived video. During the filtering process, a series of filtering mask is generated based on temporal and spatial statistics of predictive encoded video information, which is then recursively applied to the video in order to gate filtered or unfiltered video to an output channel according to coefficients of the masks. The filtering mask effectively yields a decision or rule-based map that transforms the video on a pixel-by-pixel basis thereby avoiding complex and processor-intensive decision tree logic customarily required to process individual pixels of successive macroblocks that may have different filtering requirements.

Abstract: A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes. This data cache includes a plurality of input ports for receiving the LDPC codes from some of the processing units, and a plurality of output ports for sending the LDPC codes to others of the processing units. An off-chip, external memory stores the LDPC codes and transmits the LDPC codes to and receives the LDPC codes from at least some of the processing units. A sequence processor controls the transmission of the LDPC codes between the processor units and the on-chip data cache so that the LDPC codes are processed by the processing units according to a given sequence.

Abstract: A computer readable medium is provided embodying instructions executable by a processor to perform a method for caching video data in a two-dimensional cache. The method includes storing the video data in the two-dimensional cache, addressing stored video data in the two-dimensional cache using a first tag for referencing video data of a first dimension, addressing the stored video data in the cache in terms of a second tag for referencing video data of a second dimension, and retrieving and outputting a portion of the stored video data from the two-dimensional cache according to one of the first tag and the second tag.

Abstract: A method and apparatus, particularly suited to SIMD instruction sets, to filter streaming video information encoded under a predictive encoding algorithm specified under video encoding standards, such as MPEG 4 or H.264/AVC. The filtering operation de-blocks or removes unwanted borders in the perceived video. During the filtering process, a series of filtering mask is generated based on temporal and spatial statistics of predictive encoded video information, which is then recursively applied to the video in order to gate filtered or unfiltered video to an output channel according to coefficients of the masks. The filtering mask effectively yields a decision or rule-based map that transforms the video on a pixel-by-pixel basis thereby avoiding complex and processor-intensive decision tree logic customarily required to process individual pixels of successive macroblocks that may have different filtering requirements.

Abstract: A method and apparatus, particularly suited to SIMD instruction sets, to filter streaming video information encoded under a predictive encoding algorithm specified under video encoding standards, such as MPEG 4 or H.264/AVC. The filtering operation de-blocks or removes unwanted borders in the perceived video. During the filtering process, a series of filtering mask is generated based on temporal and spatial statistics of predictive encoded video information, which is then recursively applied to the video in order to gate filtered or unfiltered video to an output channel according to coefficients of the masks. The filtering mask effectively yields a decision or rule-based map that transforms the video on a pixel-by-pixel basis thereby avoiding complex and processor-intensive decision tree logic customarily required to process individual pixels of successive macroblocks that may have different filtering requirements.

Abstract: The present invention provides methods, systems and apparatus to control instruction sequencing for a vector processor in a parallel processing environment. It enhances standard Vector Processing architectures by using two independent processing units working in conjunction to produce a highly efficient data processing ensemble. In an example embodiment, the two processors include a Scalar Processor and a separate Vector Processor. The Scalar Processor has its own Instruction Store, General Purpose Registers and Arithmetic Logic Unit. It can execute a standard instruction set including branch and jump instructions. It's function is to control the processing sequence of the Vector Processor. The Vector Processor has an independent Instruction Store, a dedicated Register along with dedicate functional elements to perform vector operations.

Abstract: A method and apparatus, particularly suited to SIMD instruction sets, to filter streaming video information encoded under a predictive encoding algorithm specified under video encoding standards, such as MPEG 4 or H.264/AVC. The filtering operation de-blocks or removes unwanted borders in the perceived video. During the filtering process, a series of filtering mask is generated based on temporal and spatial statistics of predictive encoded video information, which is then recursively applied to the video in order to gate filtered or unfiltered video to an output channel according to coefficients of the masks. The filtering mask effectively yields a decision or rule-based map that transforms the video on a pixel-by-pixel basis thereby avoiding complex and processor-intensive decision tree logic customarily required to process individual pixels of successive macroblocks that may have different filtering requirements.

Abstract: A sequential process-pipeline has a first processing stage (30) coupled to a CODEC (24) through a plurality of buffers, including an image data input buffer (28), an image data output buffer (26), and an address buffer (34). The image data input buffer stores, for each block of image data, control information for controlling the processing of an associated block of image data. The address buffer stores addresses, each of which identifies an initial address of a block of addresses within an image memory (22). A local controller (18) is responsive to the writing of an address into the address buffer to read the control information for a block to be processed, and to initiate the operation of the CODEC, in accordance with the read-out information, to execute a Discrete Cosine Transformation Process and a Discrete Cosine Transformation Quantization Process.

Abstract: A method for computing n-dimensional decomposable image transformation using the 1D approach with constrained transpose memory provides a minimized rounding/truncation error. The method minimizes transpose memory size required to fulfill a defined accuracy requirement for n-dimensional image transformation. A set of input data elements are stored. Then, a first transform, of the multiple dimension transform, is performed on the set of input data elements so as to form an array of transformed data elements, each of the transformed data elements having a larger number of bits than the input data elements. A common range of the transformed data elements is determined, and a minimum number of bits required to represent the common range without loss of information is then determined. The memory word size available for storage of the transformed data elements is compared with a minimum number of bits so as to determine an excess number of bits.

Abstract: The present invention provides an integrated display system for multi-media workstations wherein graphics image and video data are merged in a single frame buffer. The integrated display system employs 3-port VRAMs with a first serial access port for display data output, and a random access port for graphics data, a second serial access for video data input. The display system includes a single frame buffer memory system for a multi-media workstation which operates compatibly with display systems and logic designed for dual frame buffer systems and it uses the 3-port VRAM in combination with a means incorporating improved input locking, video update or refresh, and encoded video data input stream.

Abstract: A sequential process-pipeline (12) has a first processing stage (30) coupled to a CODEC (24) through a plurality of buffers, including an image data input buffer (28), an image data output buffer (26), and an address buffer (34). The address buffer stores addresses, each of which identifies an initial address of a block of addresses within an image memory (22). Each block of addresses in the image memory stores a block of decompressed image data. A local controller (18) is responsive to the writing of an address into the address buffer to initiate the operation of the CODEC to execute a Discrete Cosine Transformation Process and a Discrete Cosine Transformation Quantization Process.

Abstract: An apparatus and method for displaying non-obscured pixels in a multiple-media motion video environment (dynamic image management) possessing overlaid windows. In an encoding process, only boundary values and identification values corresponding to each window on a screen are saved in memory of a hardware device. In a decoding process, the hardware device utilizes these initial boundary values saved in memory in such a way that when incoming video data enters the hardware device, the hardware device need only compare the incoming video data's identification with the identification saved in memory. The hardware device includes: compare logic devices, counters, minimal memory devices, a control logic block, and a driver.