Abstract: A pharmaceutically acceptable composition and method for entering a cell nucleus utilizes a cell nucleus-entering polypeptide including at least one of amino acid sequence LKKTET (SEQ ID NO: 1), amino acid sequence LKKTNT (SEQ ID NO: 2) or amino acid sequence KSKLKK (SEQ ID NO: 3), or a conservative variant thereof, linked to a physiologically active agent having at least one of therapeutic or diagnostic application in the cell nucleus.

Abstract: A pharmaceutically acceptable composition and method for entering a cell nucleus utilizes a cell nucleus-entering polypeptide including at least one of amino acid sequence LKKTET (SEQ ID NO:1), amino acid sequence LKKTNT (SEQ ID NO:2) or amino acid sequence KSKLKK (SEQ ID NO:3), or a conservative variant thereof, linked to a physiologically active agent having at least one of therapeutic or diagnostic application in the cell nucleus.

Abstract: A composition including an oxidized or superoxidized methionine-containing beta thymosin peptide, isoform thereof, fragment thereof, isolated R-enantiomer thereof or isolated S-enantiomer thereof, other than racemic thymosin beta 4 sulfoxide, or a modified beta thymosin peptide, isoform or fragment thereof with an amino acid substituent substituted for at least one methionine of an amino acid sequence of a normally methionine-containing beta thymosin peptide, isoform or fragment thereof, and method for forming same.

Abstract: A method of treatment for promoting regeneration or repair a damaged cardiovascular tissue, or for preventing damage to cardiovascular tissue, includes administering to the tissue a damage-treating or -preventing fragment of thymosin beta 4 (T?4), such as AcSDKP, or a stimulating agent that forms such a fragment of (T?4).

Abstract: A pharmaceutically acceptable composition and method for entering a cell nucleus utilizes a cell nucleus-entering polypeptide including at least one of amino acid sequence LKKTET, amino acid sequence LKKTNT or amino acid sequence KSKLKK, or a conservative variant thereof, linked to a physiologically active agent having at least one of therapeutic or diagnostic application in the cell nucleus.

Abstract: A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.

Abstract: The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2N bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.

Abstract: A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.

Abstract: A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.

Abstract: The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2N bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.

Abstract: An apparatus and method for performing conversion of graphical data format is disclosed. A matrix multiplication is performed on a first set of data and a second set of data to generate a third set of data in a first format. The first and second sets of data represent the graphical data. The third set of data in the first format is transmitted to a graphics card. The third set of data in the first format is converted to a converted set of data in a second format.

Abstract: A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.

Abstract: An apparatus and method for performing an intra-add operation on packed data using computer-implemented steps is described. A processor is coupled to a hardware unit which transmits data representing graphics to another computer or display. A storage device coupled to the processor, has stored therein a routine, which, when executed by the processor, causes the processor to generate the data. The routine causes the processor to at least access a first packed data operand having at least one pair of data elements; swap positions of the data elements within the at least one pair of data elements to generate a second packed data operand, add data elements starting at the same bit positions from the first and second packed data operands to generate a third packed data operand.

Abstract: An apparatus and method for performing vertical parallel operations on packed data is described. A first set of data operands and a second set of data operands are accessed. Each of these sets of data represents graphical data stored in a first format. The first set of data operands is convereted into a converted set and the second set of data operands is replicated to generate a replicated set. A vertical matrix multiplication is performed on the converted set and the replicated set to generate transformed graphical data.

Abstract: The present invention discloses a method and apparatus for encoding an instruction in an instruction set which uses a prefix code to qualify an existing opcode of an existing instruction. An opcode and an escape code are selected. The escape code is selected such that it is different from the prefix code and the existing opcode. The opcode, the escape code, and the prefix code are combined to generate an instruction code which uniquely represents the operation performed by the instruction.