Abstract: Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ? of a 1× DDR3 clock period.

Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

Abstract: The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.

Abstract: A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

Abstract: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: The invention provides a method and apparatus for providing a uniform output from an optical transmitter. The invention comprises at least one discrete light source (30), and a housing (38) defining an internally reflecting volume (42) for light from the at least one light source, the housing having a light exit aperture (46) for light from the at least one light source. The reflecting volume is adapted to produce in an extended image surface multiple reflected images (50) of the at least one light source, and the light exit aperture is arranged to emit light from the multiple reflected images. An output lens (48) is employed in front of the light exit aperture for controlling the angular distribution of the light emitted from the at least one light source and the multiple reflected images by way of the light exit aperture.

Abstract: The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

Abstract: The invention provides an optical collection device (26) comprising a first stage optical concentrating device (34) and a second stage optical collection unit (40) having a housing (42) and an array of individual light collecting elements (46) in the housing. The array of light collecting elements provide, in combination, a light entrance and a light exit, each light collecting element having a light entrance aperture (62), a light exit aperture (64), and a light collecting region (44) extending between the entrance aperture and the exit aperture. The light collecting region provides a tapering light reflecting surface (66) arranged to direct light received at the entrance aperture towards the exit aperture. The invention also provides an optical receiver (20) comprising such an optical collection device and having at least one detecting element (24, 72, 74) arranged behind the light exit apertures to detect light transmitted by the optical collection unit.

Abstract: A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: A method for providing programmable delay read data strobe gating with voltage and temperature compensation. The method includes receiving a training request. The method further includes calibrating programmable delay lines for operating frequency and voltage and temperature variation. The method further includes locking to a first feedback signal. The method further includes storing a first feedback lock setting corresponding to the locked-to first feedback signal. The method further includes granting the training request. Additionally, when training is completed, the method further includes recalibrating the programmable delay lines for operating frequency and voltage and temperature variation.

Abstract: The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO (First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM (Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

Abstract: A tool reduces a flow of liquid or gas through a conduit. The tool includes a crimping section having a first crimping member with a first blunt section extending partially along an edge thereof and a second crimping member having a second blunt section extending partially along an edge thereof. The first and second members are pivotally engaged with one another. A handle section is connected to the crimping section. The handle section includes a first handle member connected to the first crimping member and a second handle member connected to the second crimping member. A hinge pivotally connects the first handle member to the second handle member. When the first and second handle members are pivoted about the hinge, the first and second crimping members are caused to pivot in a direction opposite to the respective first and second handle members.

Abstract: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: Inverse function of min*:min*? (inverse function of max*:max*?). Two new parameters are employed to provide for much improved decoding processing for codes that involve the determination of a log corrected minimal and/or a log corrected maximal value from among a number of possible values. Examples of some of the codes that may benefit from the improved decoding processing provided by the inverse function of min*:min*? (and/or inverse function of max*:max*?) include turbo coding, parallel concatenated trellis coded modulated (PC-TCM) code, turbo trellis coded modulated (TTCM) code, and low density parity check (LDPC) code among other types of codes. The total number of processing steps employed within the decoding of a signal is significantly reduced be employing the inverse function of min*:min*? (and/or inverse function of max*:max*?) processing.

Abstract: The invention relates to a combination which comprises a DPP-IV inhibitor and at least one further antidiabetic compound, preferably selected from the group consisting of insulin signalling pathway modulators, like inhibitors of protein tyrosine phosphatases (PTPases), non-small molecule mimetic compounds and inhibitors of glutamine-fructose-6-phosphate amidotransferase (GFAT), compounds influencing a dysregulated hepatic glucose production, like inhibitors of glucose-6-phosphatase (G6Pase), inhibitors of fructose-1,6-bisphosphatase (F-1,6-BPase), inhibitors of glycogen phosphorylase (GP), glucagon receptor antagonists and inhibitors of phosphoenolpyruvate carboxykinase (PEPCK), pyruvate dehydrogenase kinase (PDHK) inhibitors, insulin sensitivity enhancers, insulin secretion enhancers, ?-glucosidase inhibitors, inhibitors of gastric emptying, insulin, and ?2-adrenergic antagonists, for simultaneous, separate or sequential use in the prevention, delay of progression or treatment of conditions mediated by dipep

Abstract: The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.

Abstract: The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline write pointer, the second write pointer being an online write pointer. The method further includes swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static. The method further includes regenerating a DQS (Data Strobe Signal) clock.