Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.

Abstract: A method for operating a gas scrubber is disclosed in which components are removed from a crude gas by scrubbing with a chemical or physical scrubbing medium to obtain a pure gas present at elevated pressure which, after heating, is introduced into an expansion machine which after work-performing decompression the pure gas leaves at an exit temperature. The amount of heat supplied to the pure gas during heating thereof is deliberately altered to approximate the exit temperature thereof to a predetermined target value at all times.

Abstract: A method for operating a gas scrubber is disclosed in which components are removed from a crude gas by scrubbing with a chemical or physical scrubbing medium to obtain a pure gas present at elevated pressure which, after heating, is introduced into an expansion machine which after work-performing decompression the pure gas leaves at an exit temperature. The amount of heat supplied to the pure gas during heating thereof is deliberately altered to approximate the exit temperature thereof to a predetermined target value at all times.

Abstract: Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.

Abstract: A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.

Abstract: Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element.

Abstract: Detection device for detecting at least one fault state includes at least one tracer unit that includes, in at least one operating state, at least one specifically added tracer substance, and at least one detection unit for detecting a portion of material that has been released from the at least one tracer substance.

Abstract: A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The counter counts the number of clock cycles since the previous store operation, and if enabled by the user, provides a binary signal to the memory that indicates the number of clock cycles since the previous store operation, which the memory stores with the state data. If the counter overflows before a store operation is requested, the timestamp logic may force a store operation so that the time between stores can be determined.

Abstract: A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes a loop detector logic which receives incoming program counter (PC) data and detects when software loops exist. When a software loop is detected, the loop detector may be configured to store the first loop in memory, while all subsequent iterations are not stored, thus saving space in memory which would otherwise be consumed. The loop detector comprises a content addressable memory (CAM) which is enabled by a user programmed signal. The CAM may be configured with a programmable mask to determine which bits of the incoming PC data to compare with the CAM entries. The depth of the CAM also is programmable, to permit the CAM to be adjusted to cover the number of instructions in a loop.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The counter counts the number of clock cycles since the previous store operation, and if enabled by the user, provides a binary signal to the memory that indicates the number of clock cycles since the previous store operation, which the memory stores with the state data. If the counter overflows before a store operation is requested, the timestamp logic may force a store operation so that the time between stores can be determined.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes a loop detector logic which receives incoming program counter (PC) data and detects when software loops exist. When a software loop is detected, the loop detector may be configured to store the first loop in memory, while all subsequent iterations are not stored, thus saving space in memory which would otherwise be consumed. The loop detector comprises a content addressable memory (CAM) which is enabled by a user programmed signal. The CAM may be configured with a programmable mask to determine which bits of the incoming PC data to compare with the CAM entries. The depth of the CAM also is programmable, to permit the CAM to be adjusted to cover the number of instructions in a loop.