Abstract: An electronic unit for a vehicle, comprising surface elements arranged next to one another with a visible surface side and a surface underside is disclosed. The surface elements are fixed in a housing. The housing has a top side facing the surface underside and an underside, wherein a carrier plate is provided. Each housing on its underside has at least one protruding fixing element for fixing the surface elements to the carrier plate. The carrier plate connects the surface elements together, wherein each fixing element has an index element arranged on the fixing element between the carrier plate and the underside and is releasably connected to the fixing element. The index elements are connected to the carrier plate by substance bonding so each surface element is releasably fixed to the carrier plate, and wherein by the index elements, the surface elements are arranged relative to and level with one another.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: A system for determining an applicable CPT code for the patient encounter. The system, in one form, includes a paper form defining a history section, an examination section and a complexity section. Each of the history and examination sections includes a plurality of point indicators, each of which is associated with a characteristic relating to a corresponding one of the sections. Each of the point indicators is marked during the patient encounter when the associated characteristic is applicable to the patient. Each of the history and examination sections also includes a section score calculator, which records a section tally of the marked point indicators and directs the conversion of the section tally to a section score. A final code calculator records the section score for each of the history and examination sections and a section score for the complexity section, and computes a final CPT code from the sections scores.

Abstract: The invention relates to a method for testing the functionality of a spectrometer for faults comprising at least one radiation source, one filter arrangement for separating the radiation into different wavelength ranges, and one receiving arrangement. The invention also relates to a spectrometer comprising a fault recognition device. Reference values are generated at at least two different color temperatures of the radiation source and in the different wavelength ranges. Actual received signals at at least two color temperatures to be set are compared with the reference values in order to test the spectrometer. In the occurrence of variations, the type of variation is determined according to the wavelength ranges and the color temperatures, and definite faults are concluded from the type of variation.

Abstract: In a process for recognizing organic substances in solids by measuring the spectram of the radiation which is reflected or transmitted, radiation with a wavelength between 2-4 &mgr;m is used and, for radiation of solids, unmodulated radiation is used. The radiation source should have an output of at least 50 W and the distance between the illumination optics from the solid being investigated should be at least 10 cm. Recognition is based on absorption bands of the extended oscillations of C—H bonds and sometimes the presence of absorption bands of N—H bonds. Broad band radiation is preferable for radiation of the solids, and the reflected or transmitted radiation is directed through a narrow band filter with adjustable transmission frequency. This can be advantageously formed with an acousto-optical filter.

Abstract: There are proposed a method and a device for ascertaining the surface condition, particularly of traffic routes, as regards dryness, wetness or icing, in which the surface is irradiated by a radiation source with an infrared component, and the reflected radiation is measured simultaneously in different wavelength ranges characterizing water and ice. In this case at least four wavelength ranges are selected, permitting sufficient depth or penetration of the radiation into the surface. A first and a second wavelength range are so selected that they are influenced to a very small degree by absorption of the water molecules, and a third and fourth wavelength ranges are so selected that they are characteristic for water and ice. The influence of the background on signals measured in the third and fourth wavelength ranges is compensated for by means of the information in the signals measured in the first and second wavelength ranges.

Abstract: A method and apparatus for use in the recycling of post consumer or post industrial waste carpet or Polyamide-6 and/or Polyamide-66 containing non-carpet waste utilizes a hand-held portable device utilizing spectroscopic principles to accurately and quickly identify the material of the waste (carpet). The spectrometer envisioned for this task includes an infrared radiation source for illuminating the waste (carpet) sample, a selector for selecting a predetermined number of discrete wavelengths and a detection system to detect reflected radiation within the discrete wavelengths. The selector can be either a plate with a plurality of slots which positionally correspond to locations in a dispersed light beam according to the predetermined discrete wavelengths or a plurality of filters selected to pass the discrete wavelengths. The selection of the discrete wavelengths can either take place before the carpet sample is irradiated or can take place by selecting the discrete wavelengths from reflected radiation.