Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.

Abstract: An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.

Abstract: An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.

Abstract: An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract: An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract: A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.

Abstract: A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract: An integrated circuit is fabricated using photolithography by selectively exposing a photoresist layer to pattern a coarse line region of a wafer layer using a trim mask, and to pattern a fine line region of the wafer layer using an alternating phase-shift mask. The trim mask includes transparent, attenuated phase-shift and opaque regions. The phase-shifted attenuated light region patterns the coarse line region and the opaque region keeps light from exposing the fine line region. The alternating phase-shift mask patterns only the fine line region and includes one or more alternating phase-shift regions that each overlaps at least a portion of the opaque region but does not overlap the attenuated phase-shift region. The alternating phase-shift mask may be used to pattern the trim mask.