Abstract: An electronic key validation process increases security by encrypting the security access codes. A key (10) receives data having a hidden polynomial select code and polynomial seed from a host (12). A locally stored (24, 26) select offset and seed offset in the key identifies the location (22) of the select code and seed in the data. The select code decodes (32) into polynomial coefficients which are used to configure a polynomial generator (34). The seed is loaded into the polynomial generator as a starting point of the polynomial. The polynomial generator is clocked a number of cycles to calculate a remainder. The select code is modified (28) to select a new polynomial, and the polynomial generator is clocked another number of cycles. The host runs a similar encryption algorithm. The remainder is sent to the host where it is compared with the host generated remainder for key validation.

Abstract: A novel RS latch for use in asynchronous designs has been provided. The RS latch is made scannable by the use of additional circuitry which provides a basis for a scan chain signal to propagate in and out the scannable RS latch. Such a scannable RS latch greatly facilitates the testing of the asynchronous design.

Abstract: A request with response mechanism and method for a local area network controller utilizes an enable bit, a pointer, a counter and an interrupt to create the proper response to a received request with response data frame without the active aid of a host computer.

Abstract: An interface device to provide a data and address path between a data processor, a memory and peripheral devices. The interface device includes an internal arithmetic and logic unit to provide a means for generating and/or modifying addresses for the memory or peripheral devices. The device further includes a plurality of registers for temporarily storing data or addresses as well as information associated with addressing functions, for example, program counter, index register, stack pointer and page addresses. The interface device may be used singly or in combination with like devices as in a slice processing system.

Abstract: An expandable array multiplier is disclosed using an asynchronous, sequential add technique for multiplying two numbers in either straight magnitude or two's complement notation. First and second control terminals are provided for simplifying expansion to larger array sizes. The control terminals can be programmed to select either two's complement or straight magnitude multiplication. For a two's complement multiply, the control terminals are programmed according to the relative position of the particular multiplier within an expanded array such that the proper two's complement correction terms are generated within a particular multipler. A carry-lookahead technique is used to further improve multiplier performance.