Abstract: A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.

Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

Abstract: The present invention features a new and useful magnetic device and methods of its use for isolation, enrichment, and purification of cells, proteins, DNA, and other molecules. In general the device includes magnetic regions or obstacles to which magnetic particles can bind. The chemical groups, i.e., capture moieties, on the surface of the magnetic particles may then be used to bind particles, e.g., cells, or molecules of interest from complex samples, and the bound species may then be selectively released for downstream collection or further analysis.

Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.

Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

Abstract: A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

Abstract: A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Abstract: A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Abstract: An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.

Abstract: A tubular fuel gas-steam reformer assembly, preferably an autothermal reformer assembly, for use in a fuel cell power plant, includes a fuel-steam vaporizer, a fuel-steam and air mixing station, and a catalyst bed. The catalyst bed can include catalyzed alumina pellets, or a monolith such as a foam or honeycomb body which is preferably formed from a high temperature material such as a steel alloy, or from a ceramic material. The fuel-steam mixture is vaporized in the vaporizer and then passes into the mixing station. The mixing station comprises a plurality of mixing tubes which open into the catalyst bed. The mixing tubes extend through a manifold and include openings which interconnect the interior of the tubes with the manifold. The openings have axes which are perpendicular to the axis of each of the mixing tubes, and are positioned on the tubes at locations which are dictated by the diameter of the mixing tubes and which will ensure thorough mixing of the air and fuel-steam streams.

Abstract: A method for suppressing noise in a turbofan engine includes segmenting coaxial inner and outer flow streams into circumferentially interleaved inner and outer segments beginning at a common location along the engine axis, diverting additional portions of the outer stream radially inwardly from an axial location downstream of the common location and combining the inner segments, the outer segments and the additional portions into a common stream so that the additional portions are introduced into discrete radial locations in the common stream. The diverted additional portions of the outer stream eliminate localized regions of hot, high velocity gases in the combined stream to achieve improved noise suppression.

Abstract: A lobed mixer has major and minor lobes. The major lobes increase in both height and width in the downstream axial direction. Each major lobe has two minor lobes positioned on its radially outer surface located downstream of the beginning of the major lobe. The radial depth of the minor lobes increases with downstream axial distance but is never greater than the depth of the major lobes. Each of the chutes formed between the minor lobes introduces an additional stream of cold, low velocity fan flow into the hot, high velocity core flow to improve the uniformity of mixing. The double lobed mixer decreases acoustic intensity while having little or no effect on engine performance.