Patents by Inventor Thomas J. Best

Thomas J. Best has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953981
    Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: April 9, 2024
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
  • Patent number: 8493119
    Abstract: Embodiments of a scannable flip-flop are disclosed that may reduce data hold time, which may in turn improve the performance of circuits incorporating the scannable flip-flop. The scannable flip-flop may include a slave latch and a master latch including an input multiplexer. The multiplexer may include a number of input ports, for example to receive normal operating mode data as well as scan operating mode data, and the multiplexer may be operable to controllably select one of the input ports and pass the value of the selected port to an output of the multiplexer. For example, the multiplexer may generate individual control signals for the various ports dependent upon both the clock signal and a select signal, such that each of the ports is qualified with the select signal and the clock signal before the multiplexer presents the input data of the selected port as the output of the multiplexer.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 23, 2013
    Assignee: Apple Inc.
    Inventors: Derrick A. Leach, Thomas J. Best, Edward M. McCombs
  • Publication number: 20120146697
    Abstract: Embodiments of a scannable flip-flop are disclosed that may reduce data hold time, which may in turn improve the performance of circuits incorporating the scannable flip-flop. The scannable flip-flop may include a slave latch and a master latch including an input multiplexer. The multiplexer may include a number of input ports, for example to receive normal operating mode data as well as scan operating mode data, and the multiplexer may be operable to controllably select one of the input ports and pass the value of the selected port to an output of the multiplexer. For example, the multiplexer may generate individual control signals for the various ports dependent upon both the clock signal and a select signal, such that each of the ports is qualified with the select signal and the clock signal before the multiplexer presents the input data of the selected port as the output of the multiplexer.
    Type: Application
    Filed: November 14, 2011
    Publication date: June 14, 2012
    Inventors: Derrick A. Leach, Thomas J. Best, Edward M. McCombs