Patents by Inventor THOMAS J. BUCELOT

THOMAS J. BUCELOT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141915
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Publication number: 20170207772
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Application
    Filed: April 5, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9705479
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9634654
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9618966
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Patent number: 9612614
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Patent number: 9612612
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Patent number: 9571100
    Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, David W. Shan, Mrigank Sharad
  • Publication number: 20170040987
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 9, 2017
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Publication number: 20170040981
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Application
    Filed: August 18, 2015
    Publication date: February 9, 2017
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Publication number: 20170031384
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Application
    Filed: August 18, 2015
    Publication date: February 2, 2017
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Publication number: 20170031383
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Publication number: 20160105177
    Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Inventors: ADITYA BANSAL, THOMAS J. BUCELOT, ALAN J. DRAKE, PHILLIP J. RESTLE, DAVID W. SHAN, MRIGANK SHARAD
  • Patent number: 9276563
    Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, David W. Shan, Mrigank Sharad
  • Publication number: 20150365076
    Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: ADITYA BANSAL, THOMAS J. BUCELOT, ALAN J. DRAKE, PHILLIP J. RESTLE, DAVID W. SHAN, MRIGANK SHARAD
  • Publication number: 20150234422
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 20, 2015
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G.R. Thomson
  • Patent number: 9058130
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Patent number: 9054682
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Publication number: 20140223210
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G.R. Thomson
  • Publication number: 20140218087
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G.R. Thomson