Patents by Inventor Thomas J. Cummings

Thomas J. Cummings has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953547
    Abstract: An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 9, 2024
    Assignee: BAE Systems Controls Inc.
    Inventors: Thomas J. Cummings, Robert J. Vovos
  • Patent number: 11934161
    Abstract: System and method provide wireless distributed lighting control systems implementing a secure peer-to-peer, self-organizing and self-healing mesh network of actuators and system inputs. The system and method can be designed specifically for indoor and outdoor lighting where actuators include in-fixture, on-fixture and circuit control modules with ON/OFF and full range dimming capabilities, and system inputs include occupancy/vacancy sensors, daylight sensors and switches. A unique messaging protocol facilitates wireless and wired communication between actuators and system inputs, and provides web-based commissioning and monitoring of the lighting control system using a wireless access point accessible from a local network or Internet which can provide an intuitive and easy to use Graphical User Interface (GUI).
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 19, 2024
    Assignee: HLI SOLUTIONS, INC.
    Inventors: Theodore E. Weber, Terrence R. Arbouw, Ronald K. Bender, Ronald J. Cummings-Kralik, Michael D. Crane, Thomas J. Hartnagel, Robert A. Martin, Peter A. Moyle, Gregory F. Smith, Stephan K. Zitz
  • Publication number: 20230349984
    Abstract: A power supply includes an I/O module configured to receive a high voltage DC input and output a high voltage DC, a plurality of DC converter modules configured to receive the high voltage DC output from the I/O module and output a low voltage DC output, and a plurality of AC inverter modules configured to receive the high voltage DC output from the I/O module and output a high voltage AC output. Each of the plurality of DC converter modules, each of the plurality of AC inverter modules and the I/O module may be mounted in a corresponding individual chassis. Each of the individual chassis may be configured to be stackable together into a single line replaceable unit (LRU). Each of the individual chassis may have an identically shaped outer frame.
    Type: Application
    Filed: February 24, 2021
    Publication date: November 2, 2023
    Inventors: Thomas J. Cummings, Peter A. Carruthers, David J. Czebiniak, John P. Zielinski
  • Publication number: 20230204665
    Abstract: An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: BAE Systems Controls Inc.
    Inventors: Thomas J. Cummings, Robert J. Vovos
  • Patent number: 10903834
    Abstract: An electronic power device formed by a plurality of FETs formed on a circuit board formed of a plurality of layers, the plurality of transistors being formed on a first surface of the circuit board, the plurality of layers including a plurality of gate drive layers, a plurality of gate return layers, and a plurality of power layers. A gate drive circuit is formed on a second surface of the circuit board, the second surface being opposite the first surface, the gate drive circuit being connected to the gate and source of each of the plurality of transistors through the plurality of gate drive layers and the plurality of gate return layers. A voltage supply is connected to the drain of each of the plurality of transistors, the connections of the voltage supply to each of the plurality of transistors being interleaved through the plurality of power layers.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: January 26, 2021
    Assignee: BAE Systems Controls Inc.
    Inventors: Nicholas A. Lemberg, Andrew S. Clark, Thomas J. Cummings, Robert J. Vovos
  • Patent number: 10586325
    Abstract: A method of determining delamination in a transistor is disclosed including loading a grey scale image of an transistor into memory, generating a black and white image based on the loaded grey scale image, identifying boundaries within the generated black and white image, cropping the black and white image based on the identified boundaries, identifying at least one feature in the cropped black and white image based on the identified boundaries, normalizing the cropped black and white image based on an attribute of the identified at least one feature, cropping the grey scale image based on the normalized black and white image, comparing the cropped grey scale image to a baseline grey scale image of the transistor, and determining a change in a percentage of delamination of the transistor between the baseline grey scale image and the cropped grey scale image based on the comparison.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 10, 2020
    Assignee: BAE Systems Controls Inc.
    Inventors: Thomas J. Cummings, Joseph D. Cipollina
  • Publication number: 20190206039
    Abstract: A method of determining delamination in a transistor is disclosed including loading a grey scale image of an transistor into memory, generating a black and white image based on the loaded grey scale image, identifying boundaries within the generated black and white image, cropping the black and white image based on the identified boundaries, identifying at least one feature in the cropped black and white image based on the identified boundaries, normalizing the cropped black and white image based on an attribute of the identified at least one feature, cropping the grey scale image based on the normalized black and white image, comparing the cropped grey scale image to a baseline grey scale image of the transistor, and determining a change in a percentage of delamination of the transistor between the baseline grey scale image and the cropped grey scale image based on the comparison.
    Type: Application
    Filed: January 2, 2018
    Publication date: July 4, 2019
    Applicant: BAE Systems Controls Inc.
    Inventors: Thomas J. Cummings, Joseph D. Cipollina