Abstract: An integrated circuit system (120) includes a memory array (122) storing a configuration data set to configure an integrated circuit. The integrated circuit (121) includes a configuration memory (128) and a configuration controller state machine (126). The configuration controller state machine operates so as to read a read-check signature at a read-check address of the memory array (122) and to compare the read-check signature with a standard signature stored in the integrated circuit (121). If the read-check signature passes the comparison, the configuration controller state machine (126) loads the configuration data set from the memory array to the configuration memory (128) of the integrated circuit.

Abstract: Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.

Abstract: Described are area-efficient non-volatile memory systems. Non-volatile memory cells in these systems include only one transistor, two fewer than conventional non-volatile memory cells, and reduced interconnect. The simplicity of the memory cells reduces memory-system area, improves manufacturing yield, and consequently reduces cost. New program, erase, and read methodologies have been developed for use with the simplified memory cells.

Abstract: A non-volatile product term cell is provided having a first floating gate located over a first p-channel transistor and a first n-channel transistor, and a second floating gate located over a second p-channel transistor and a second n-channel transistor. A control gate is located over the first and second floating gates. A first tunnel oxide capacitor is coupled to the first floating gate and a second tunnel oxide capacitor is coupled to the second floating gate. A first transistor pair is coupled between the first p-channel transistor and the second n-channel transistor, and a second transistor pair is coupled between the second p-channel transistor and the first n-channel transistor. The first and second floating gates are programmed and/or erased. Complementary input signals are applied to the first and second transistor pairs. An output signal is provided in response to the programmed/erased states of the first and second floating gates.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: A level shifter for low voltage operation includes two level shifting stages. The first stage shifts the input voltage level to an intermediate voltage level, and the second stage shifts the intermediate voltage level to an output voltage level. This two-stage arrangement allows the level shifter to function for very low input voltages, and enables functionality across a wide range of output voltages. The first stage is designed to be compatible with very low input voltages and the intermediate voltage level is chosen to be within the safe operating limits of the first stage. The intermediate voltage level is also high enough to drive the high voltage devices of the second stage. This level shifter can be used where multiple output voltage levels are required depending on the particular application or operating mode.

Abstract: Described are circuits and methods for automatically measuring the program threshold voltage VTP and the erase threshold voltage VTE of EEPROM cells. The measured threshold voltages are employed to measure tunnel-oxide thickness and to determine optimal program and erase voltage levels for EEPROM circuits. One embodiment automatically sets the program and erase voltages based on the measured threshold voltages.

Abstract: A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data while the CPLD is operating in a first configuration. This relatively time-consuming operation has no effect on CPLD operation since only the SRAM array controls the configuration of the CPLD. At a desired point in time, the new configuration data from the EEPROM array can be loaded into the SRAM array to reconfigure the CPLD. Because this loading of configuration data into the SRAM array takes only microseconds to perform, normal system operation effectively proceeds without interruption. A CPLD can include multiple EEPROM arrays, each storing a different set of configuration data, thereby allowing the CPLD to rapidly switch between various configurations by loading the configuration data from different EEPROM arrays into the SRAM array.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: A ramp-up circuit on an integrated circuit receives a relatively high program (erase) voltage for changing the program state of a memory cell. The ramp-up circuit gradually raises the program (erase) voltage to prevent damage to the memory cell. The ramp-up circuit includes a pass gate and associated control circuitry that provides a controlled, ramped-up version of the program (erase) voltage to the memory cell without raising internal circuit nodes above the program (erase) voltage.

Abstract: A non-volatile, in-system programmable integrated-circuit switch has horizontal conductive lines and vertical conductive lines. A programmable interconnect cell including a floating gate transistor is provided at each intersection of a horizontal line and a vertical line. Each line is connected to a pin through a programmable I/O cell which includes a floating gate transistor. Each I/O cell can be programmed to configure the corresponding pin as an input pin or as an inverting or non-inverting output pin. The I/O cell can also be programmed to tri-state the pin or to fix the pin at a high or low voltage level. Each input pin can be connected to more than one output pins. A TTL-to-CMOS translator in each I/O cell is provided in the output section of the cell to reduce the translator output load and make the load, and hence the speed and power consumption of the switch, less dependent on the switch programming.

Abstract: A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

Abstract: A structure and method are provided wherein a single output buffer stage (50) is provided which can be programmed to function either as an open drain output buffer or a CMOS Push-Pull output buffer. The output buffer stage constructed in accordance with this invention is programmed in one of several manners. In one embodiment of this invention, the fabrication steps utilized to program the output buffer are the enhancement and depletion dopings, whereby certain devices of the output buffer are programmed to either remain always turned off or always turned on, thus programming the output buffer to serve either as an open drain output buffer or as a CMOS push-pull output buffer.

Abstract: A simple six-transistor input buffer for generating and applying binary function test signals to associated circuitry in an integrated circuit package. The buffer recognizes three different voltage levels of an input signal that is applied to a single input test pin and generates three corresponding binary output signals that may be used for testing various functions of the associated circuitry.

Abstract: A digitally synthesized frequency back-up circuit which, after removal or failure of applied A.C. power, will reproduce signals precisely indicative of each zero transition point of the A.C. waveform. A high frequency binary counter continually counts internally generated pulses and at the end of each A.C. period, stores one-half the count, representing 180.degree. , in a storage buffer. When the A.C. fails, the inverted value of the buffer count is loaded into the counter which is incremented by the internally generated pulses to count only up to the value stored in the buffer, at which point the circuit generates an output pulse. As long as the A.C. frequency remains off, the counter will continue to reload from the buffer and count the value representing this 180.degree. period. An additional and separate buffer section in the circuit stores the binary count representing the 90.degree. point in each A.C. cycle and continuously generates 90.degree.

Abstract: A digital circuit for sensing the signal on a data bus, selectively incrementing or decrementing the binary signal and reapplying it to the bus. The circuitry includes a binary counter comprising a temporary storage cell for each bus conductor. The output of each cell controls the conduction through an adjacent portion of a pre-charged conductor which is periodically discharged at the least significant digit cell and which, when charged adjacent a higher order cell, will inhibit the toggling of that cell. All bus lines are pre-charged to a binary "1" at a particular instant followed by the discharge to "0" of those lines whose respective cells contain a binary "0".