Abstract: A system and computer program product for controlling the allocation of shared resources. The system includes a next request priority module connected to a shared resource and to a plurality of requesters identified by requester identifiers. The next request priority module includes a pending request mechanism that prioritizes pending requests for the shared resource, a logging mechanism logging requester identifiers associated with previous grants to the shared resource, and next request priority logic. The next request priority logic accesses the next pending request to determine if it should be granted priority to the shared resource. The determining is responsive to logged requester identifiers and to the next requester identifier. Priority is granted to the shared resource to the next pending request in response to determining that the next pending request should be granted priority to the shared resource. The next requester identifier is logged in response to the granting.

Abstract: A computer implemented method for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread. A string of instructions to complete a transaction of the first thread are executed, beginning with one instruction of the string of instructions. It is determined whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread. A cache structure and a transaction table which together provide for entries in an active mode for the AIG are located if the one instruction is part of an active AIG. The next instruction is executed under a normal execution mode in response to determining that the one instruction is not part of an active AIG.

Abstract: Embodiments related to a transaction program. An aspect includes, based on determining that one instruction is part of an active atomic instruction group (AIG), determining whether a private-to-transaction (PTRAN) bit associated with an address of the one instruction in a main memory is set, the PTRAN bit being located in a main memory comprising a plurality of memory increments each having a respective directly addressable PTRAN bit in the main memory. Another aspect includes, based on determining that the PTRAN bit is not set: setting the PTRAN bit; adding a new entry to a cache structure and a transaction table including an old data state of the address of the one instruction stored in the cache structure and control information stored in the transaction table; and completing the one instruction as part of the active AIG.

Abstract: Embodiments related to a hardware transactional memory (HTM). An aspect includes setting a mode register of a processor core of a computer to indicate a HTM mode. Another aspect includes executing a plurality of transactions by the processor core in the HTM mode based on the mode register. Another aspect includes determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode. Yet another aspect includes, based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode.

Abstract: A computer program product for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread. A string of instructions to complete a transaction of the first thread are executed, beginning with one instruction of the string of instructions. It is determined whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread. A cache structure and a transaction table which together provide for entries in an active mode for the AIG are located if the one instruction is part of an active AIG. The next instruction is executed under a normal execution mode in response to determining that the one instruction is not part of an active AIG.

Abstract: A computer processing system having memory and processing facilities for processing data with a computer program is a Hybrid Transactional Memory multiprocessor system with modules 1 . . . n coupled to a system physical memory array, I/O devices via a high speed interconnection element. A CPU is integrated as in a multi-chip module with microprocessors which contain or are coupled in the CPU module to an assist thread facility, as well as a memory controller, cache controllers, cache memory, and other components which form part of the CPU which connects to the high speed interconnect which functions under the architecture and operating system to interconnect elements of the computer system with physical memory, various 1/0, devices and the other CPUs of the system.

Abstract: A computer program product for initiating a task in a computer system including executing a method that includes receiving a task and a status of the task relative to a target service level. A current power state of the processor is determined. Execution of the task is initiated on the processor in response to the status indicating that the task is meeting the target service level and to the current power state being a low power state. It is determined if the processor can be moved into a high power state, the determining performed if the task is not meeting the target service level and the current power state is the low power state. If the processor can be moved into the high power state then the processor is moved into the high power state and execution of the task is initiated on the processor.

Abstract: Power management in a multi-processor computer system, including a computer program product for facilitating receiving a task for execution in a high power state, and determining a current power state of a processor in a multi-processor system, the system having a specified power limit. The task is dispatched to the processor if the current power state of the processor is the high power state. If the processor is not in the high power state, then it is determined if moving the processor into the high power state will cause the multi-processor system to exceed the specified power limit. The processor is moved into the high power state in response to determining that moving the processor into the high power state will not cause the multi-processor system to exceed the specified power limit. The task is dispatched to the processor in response to moving the processor into the high power state.

Abstract: A computing system has a stack of microprocessor chips that are designed to work together in a multiprocessor system. The chips are interconnected with 3D through vias, or alternatively by compatible package carriers having the interconnections, while logically the chips in the stack are interconnected via specialized cache coherent interconnections. All of the chips in the stack use the same logical chip design, even though they can be easily personalized by setting specialized latches on the chips. One or more of the individual microprocessor chips utilized in the stack are implemented in a silicon process that is optimized for high performance while others are implemented in a silicon process that is optimized for power consumption i.e. for the best performance per Watt of electrical power consumed. The hypervisor or operating system controls the utilization of individual chips of a stack.

Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection, of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.

Abstract: A method for controlling the allocation of shared resources that includes receiving, from a requestor executing on a processor, a request to access a shared resource. The receiving is at a next request priority module connected to the processor and the shared resource. It is determined if any of a specified number of most recent priority grants to the shared resource were to the requestor. The request is granted if none of the specified number of most recent priority grants to the shared resource were to the requestor. If any of the specified number of most recent priority grants to the shared resource were to the requestor, then it is determined if one or more other requests for the shared resource are pending. It is determined if one of the other requests should be granted priority to the shared resource if other requests for the shared resource are pending.

Abstract: A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transactions with a Transaction Table in memory for parallel processing of multiple threads of execution by support of which an application need not be aware. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.

Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution provides execution of multiple atomic instruction groups (AIGs) on multiple systems to support a single large transaction that requires operations on multiple threads of execution and/or on multiple systems connected by a network. The support provides a Transaction Table in memory and fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.

Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and performs fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. A transaction program employs a plurality of Set Associative Transaction Tables, one for each microprocessor, and Load and Store Summary Tables in memory for fast processing of common conflict.

Abstract: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Abstract: Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction.

Abstract: Power management in a multi-processor computer system, including a computer program product for facilitating receiving a task for execution in a high power state, and determining a current power state of a processor in a multi-processor system, the system having a specified power limit. The task is dispatched to the processor if the current power state of the processor is the high power state. If the processor is not in the high power state, then it is determined if moving the processor into the high power state will cause the multi-processor system to exceed the specified power limit. The processor is moved into the high power state in response to determining that moving the processor into the high power state will not cause the multi-processor system to exceed the specified power limit. The task is dispatched to the processor in response to moving the processor into the high power state.

Abstract: A computer program product for initiating a task in a computer system including executing a method that includes receiving a task and a status of the task relative to a target service level. A current power state of the processor is determined. Execution of the task is initiated on the processor in response to the status indicating that the task is meeting the target service level and to the current power state being a low power state. It is determined if the processor can be moved into a high power state, the determining performed if the task is not meeting the target service level and the current power state is the low power state. If the processor can be moved into the high power state then the processor is moved into the high power state and execution of the task is initiated on the processor.

Abstract: Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.

Abstract: A computing system has a stack of microprocessor chips that are designed to work together in a multiprocessor system. The chips are interconnected with 3D through vias, or alternatively by compatible package carriers having the interconnections, while logically the chips in the stack are interconnected via specialized cache coherent interconnections. All of the chips in the stack use the same logical chip design, even though they can be easily personalized by setting specialized latches on the chips. One or more of the individual microprocessor chips utilized in the stack are implemented in a silicon process that is optimized for high performance while others are implemented in a silicon process that is optimized for power consumption i.e. for the best performance per Watt of electrical power consumed. The hypervisor or operating system controls the utilization of individual chips of a stack.