Abstract: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.

Abstract: An apparatus for automatically linking a drive member of a power source and a driven member of an implement, includes two attachment pieces, one attached to the power source, and the other attached to the implement, and an attachment mechanism for automatically connecting the two attachment pieces whereby the drive member and the driven member are operably coupled.

Abstract: An apparatus for automatically linking a drive member of a power source and a driven member of an implement, includes two attachment pieces, one attached to the power source, and the other attached to the implement, and an attachment mechanism for automatically connecting the two attachment pieces whereby the drive member and the driven member are operably coupled.

Abstract: An apparatus for automatically linking a drive member of a power source and a driven member of an implement, includes two attachment pieces, one attached to the power source, and the other attached to the implement, and an attachment mechanism for automatically connecting the two attachment pieces whereby the drive member and the driven member are operably coupled.

Abstract: An apparatus for automatically linking a drive member of a power source and a driven member of an implement, includes two attachment pieces, one attached to the power source, and the other attached to the implement, and an attachment mechanism for automatically connecting the two attachment pieces whereby the drive member and the driven member are operably coupled.

Abstract: A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of the processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of the sequential stream of instructions by the first processing element it becomes beneficial to have the second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of the computer system which is determined by a combination of the states of the first and second processing elements.

Abstract: A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of the processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of said sequential stream of instructions by said first processing element it becomes beneficial to have the second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of said computer system which is determined by a combination of the states of said first and second processing elements.