Abstract: A programmable modulator (100) is programmable to operate in either of a GMSK or 8PSK mode. When operating in a GMSK mode, a signal modulating circuit 105 receives (210) a bit stream (110), maps the bit stream (110) to a phase value in complex I, Q form and applies a progressive rotation to the phase value according to GMSK specifications. The output (140) is filtered by a filter circuit (135), preferably using a complex Finite Impulse Response (FIR) filter using the standard coefficients for an 8PSK modulation to create (215) an approximate GMSK output (165). A GMSK correction circuit (150) determines a correction term that is added to the filter circuit output (165) so as to correct amplitude variations to allow the output to conform to GSM/EDGE standards. The same modulator (100) may be programmed to operate in an 8PSK mode with linear predistortion.

Abstract: An access point (108) in a dual-frequency TDD communication system (100) includes a transceiver (122) that transmits information to a first group of subscriber devices (104a-n) at a first frequency (f1) and contemporaneously receives information from a second group of a subscriber devices (106a-n) at a second frequency (f2) during at least a portion of a period of time (T1). The access point (108) also transmits information to the second group of subscriber devices (106a-n) at the second frequency (f2) and contemporaneously receives information from the first group of subscriber devices (104a-n) at the first frequency (f1) during at least a portion of a second period of time (T3). A method for performing a dual-frequency communication scheme is also provided.

Abstract: A communication system implements detection of bad frames of information by utilizing multiple bit correction thresholds. Equipment used within the communication system adapts to different signaling environments by dynamically altering the bit correction threshold based on a history of the number of consecutive bad frames of information that have been previously erased and the number of bits corrected by a channel decoder (202). By implementing this dynamic bit correction threshold, sufficient bad frame indication (BFI) detection and receiver sensitivity can be obtained simultaneously, which results in an improved perceived audio quality to the end user.

Abstract: A direct digital frequency synthesizer increases the frequency resolution of the analog output signal by using fractionalization techniques. The best integer value I.sub.FR of a digital signal is determined and the next integer value I.sub.FR +1 of a digital signal is used to determine a weighted fractionalized value of the digital signal. The fractionalized value of the digital signal is used to synthesize the analog output signal having increased frequency resolution. In addition, IFR and IFR+1 are optimally distributed during the weighting process to ensure a minimum cumulative phase error.