Patents by Inventor Thomas J. Makovicka

Thomas J. Makovicka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6725193
    Abstract: A voice recognition system for use with a communication system having an incoming line carrying an incoming signal from a first end to a second end operably attached to a speaker and the outgoing line carrying an outgoing signal from a microphone near the speaker. A first speech recognition unit (SRU) detects selected incoming words and a second SRU detect outgoing words. A comparator/signal generator compares the outgoing word with the incoming word and outputs the outgoing word when the outgoing word does not match the incoming word. The first SRU may be delayed relative to the second SRU. The SRU's may also search only for selected words in template, or may ignore words which are first detected by the other SRU. A signaler may also provide a signal indicating inclusion of one of the selected words in a known incoming signal with an SRU being responsive to that signal to ignore the included one command word in the template for a selected period of time.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: April 20, 2004
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Thomas J. Makovicka
  • Patent number: 6075987
    Abstract: A method is provided for determining the position of a user terminal utilizing global positioning system (GPS) satellites, each of the GPS satellites transmitting a signal containing information indicative of the orbital parameters of the respective GPS satellite, timing and synchronization data and clock correction parameters.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: June 13, 2000
    Assignee: Ericsson Inc.
    Inventors: Thomas O. Camp, Jr., Thomas J. Makovicka
  • Patent number: 4862407
    Abstract: A digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed. Coprocessors represent microcoded machines wherein low level instructions directed toward the mechanics of performing a specific signal processing algorithm are contained in microcode. Thus, the host processor programs coprocessors using higher level functional instructions. Each of the coprocessors has a multiply-accumulator, a barrel shifter, an address generator, a hardware loop counter, and a microsequencer.
    Type: Grant
    Filed: October 5, 1987
    Date of Patent: August 29, 1989
    Assignee: Motorola, Inc.
    Inventors: Bruce A. Fette, Leslie K. Lewis, Marc L. Briel, Thomas J. Makovicka