Abstract: A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

Abstract: A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

Abstract: An input biasing system for accommodating a floating power supply to the range of an input signal includes input terminals for receiving a input signal and a biasing circuit including a first impedance connected between one of the input terminals and a floating power supply and a second impedance connected between another of the input terminals and the ground of the floating power supply for bracketing the floating power supply about the input signal.

Abstract: An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with the data converter for generating a pseudo random number sequence; a signature generating circuit responsive to data exchanged between the controller and data converter for altering the pseudo random number sequence generated by the linear feedback shifter register to create a signature of the data.

Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Abstract: A multi-channel analog to digital converter which facilitates calibration of the analog to digital converter and respective input channels to the analog to digital converter, and a method for calibrating the analog to digital converter. A multi-channel ADC (1) comprising an ADC circuit (2) for converting analog signals received on input channels CH1 to CHN to digital output signals comprises a primary offset storing register (24) and a primary gain storing register (25) for storing respective primary offset and gain correction codes which are applied to the digital output signals in a primary correcting circuit (14) for correcting for the offset and gain errors introduced by the ADC circuit (2).

Abstract: An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with the data converter for generating a pseudo random number sequence; a signature generating circuit responsive to data exchanged between the controller and data converter for altering the pseudo random number sequence generated by the linear feedback shifter register to create a signature of the data.

Abstract: A clock oscillator having a pair of pins adapted for coupling to an external crystal, a first one of such pair of pins being adapted for coupling to an external clock. A switch, formed on the chip, is provided for electrically decoupling the crystal excitation circuit from one of the pair of pins in response to a control signal. In accordance with one embodiment of the invention, the switch is disposed between the output of a crystal excitation circuit and the second one of the pair of output pins and, in another embodiment, the switch is placed in circuit between the input to the crystal excitation circuit and the first one of the pair of pins. In each of these embodiments, when the switch is in a first condition, clock pulses are prevented from being coupled to the second one of the output pins, either: by preventing the external clock from feeding the input to the crystal excitation circuit; or, by preventing the output of the crystal excitation circuit from feeding the second one of the pair of pins.