Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map.

Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices. The memory controller is configured to receive a virtual to physical memory address translation map from a host device, where a physical memory address includes a physical address for memory on the host device. The memory controller is configured to store the virtual to physical memory address translation map in a memory module on the memory controller, receive commands directly from an application running on the host device, where the commands include virtual memory addresses that refer to the memory on the host device and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.

Abstract: Methods and apparatus for dispatching memory operations are disclosed. An example memory controller for controlling operation of a data storage device includes a command dispatcher that dispatches memory operation commands for execution by a plurality of memory devices. The command dispatcher includes a command buffer that separately and respectively queues the memory operation commands by maintaining a respective linked list of memory operation commands for each memory device. The command dispatcher also includes a selection circuit with a plurality of leaf nodes. Each leaf node corresponds with one of the linked lists and indicates whether its corresponding linked list includes memory operation commands awaiting dispatch. The selection circuit also includes an OR-reduction tree that reduces the plurality of leaf node indications to a root node indication. The selection circuit iterates over the nodes of the OR-reduction tree to select memory operation commands for dispatch by the command dispatcher.

Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map.

Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices. The memory controller is configured to receive a virtual to physical memory address translation map from a host device, where a physical memory address includes a physical address for memory on the host device. The memory controller is configured to store the virtual to physical memory address translation map in a memory module on the memory controller, receive commands directly from an application running on the host device, where the commands include virtual memory addresses that refer to the memory on the host device and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.

Abstract: Methods and apparatus for managing latency of memory commands are disclosed. An example method includes receiving memory operation commands for execution by a data storage device, each memory operation command being associated, for execution, with one of a plurality of memory devices. The example method also includes maintaining, for each memory device, a respective cumulative latency estimate. The example method also includes, for each memory operation command, when received by the memory controller, comparing the respective cumulative latency estimate of the associated memory device with a latency threshold for the received memory operation command. In the event the cumulative latency estimate is at or below the latency threshold, the received memory operation command is provided to a respective command queue operatively coupled with the respective memory device. In the event the cumulative latency estimate is above the latency threshold, the received memory operation command is returned to a host device.

Abstract: Shared memory device apparatus and related methods are disclosed. An example method includes obtaining memory operation commands. The memory operation commands are received by a command dispatcher in a same order as obtained by the queue arbiter from the host device. The example method further includes separately and respectively queuing the memory operation commands for each of a plurality of memory devices and dispatching the memory operation commands for execution. The example method also includes receiving the dispatched memory operation commands at a plurality of command queues, where each command queue is associated with a respective one of the plurality of memory devices. Each command queue is configured to receive its respective dispatched memory operation commands from the command dispatcher in a same order as received by the dispatcher and provide the received memory operation commands to its respective memory device in a first-in-first-out order.

Abstract: An apparatus for error correction for a data storage device may include an input interface that is configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, where each of the channel controllers is arranged and configured to control operations associated with one or more memory chips. The apparatus may include a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction using an error correction algorithm and the error correction information to generate correction solutions, where the corrector module is a shared resource for the multiple channel controllers. The apparatus may include an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers.

Abstract: An apparatus for error correction for a data storage device may include an input interface that is configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, where each of the channel controllers is arranged and configured to control operations associated with one or more memory chips. The apparatus may include a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction using an error correction algorithm and the error correction information to generate correction solutions, where the corrector module is a shared resource for the multiple channel controllers. The apparatus may include an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers.

Abstract: A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.

Abstract: A base address matching device and method are disclosed. In a switching device having a plurality of input/output ports, a routing device has been described that has an array of registers in which each register holds content associating an address with one of the input/output ports in the switching device and elements of the content in the array of registers are pre-sorted into a specified order, and an address matching element that has a plurality of comparators that are electrically coupled to selected registers in the array of registers. The base address matching element is able to select a matching address from the content of the array of registers and to direct a communication packet to one of the ports in the switch by matching the target address in the packet to an address in the content of the register in the array of registers associated with the port.