Abstract: A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.

Abstract: A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.

Abstract: A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.

Abstract: An integrated multiport switch (IMS) having a receive FIFO structure with a single port RAM, for storing network communication data received from each port of the switch. The RAM is connected to a FIFO control unit, which is coupled to a MAC for each port by a MAC bus, by a FIFO memory input bus. Writing of data received from each port via the MAC bus to the RAM is controlled on a time shared basis. The FIFO control unit includes a receive RAM interface that is connected to the MAC bus for receiving communication data from the ports and to the FIFO memory input bus for transferring communication data to the RAM for temporary storage. As the FIFO memory input bus has a larger bit transfer capacity than the MAC bus, the receive RAM interface can accumulate incoming data during clock cycles in which data is being read from the single port RAM.

Abstract: A method and arrangement for reclaiming buffers used to store frames, following the transmission of a frame, checks to determine whether the transmission of a frame is the last copy of that frame to be transmitted. If it is the last copy, or the only copy, the buffers storing that frame are reclaimed for reuse after the contents of each buffer are transmitted. If the frame is not the last copy, or it cannot be determined whether it is the last copy, then the frame is transmitted and a count of the number of transmitted copies of that frame is decremented. Once all of the copies have been transmitted, the buffer reclaiming process is initiated.

Abstract: A resetting, enabling and freezing system is provided for controlling a communication device in a diagnostic process. A hardware reset of the device may be performed by a host via a reset pin of a PCI interface. A software reset of the device may be provided by setting a reset bit in a command register. To stop operations of the device substantially instantaneously, a freeze mode of diagnostics is provided. The freeze mode may be initiated using hardware or software freezing. To provide the hardware freezing, diagnostic logic is supplied with a freeze signal via a freeze pin of the PCI interface. The software freezing is performed by setting a freeze bit in the command register. To enable a diagnostician to reproduce an event causing an error, an enable/disable mode of diagnostics is carried out. In this mode, elements of the device are disabled one after another in a serial fashion, with a disable signal being passed serially from one element to another.

Abstract: Write posting buffers and read prefetch buffers are arranged in an integrated multiport switch between a PCI interface and an external memory interface. When a PCI host initiates a PCI transaction to write data from an external memory, the data provided by the PCI host is written into the write posting buffers. Then, the contents of the write posting buffers is transferred to the external memory. The read prefetch buffers are used to temporarily store data prefetched in anticipation of a PCI transaction initiated by the PCI host to read that data from the external memory. When the PCI host initiates the read transaction, the address of the requested data is compared with the address of the prefetched data to transfer the prefetched data to the host if a match is detected. In an auto-prefetch mode, data is automatically prefetched from the external memory when an extension bus port output queue contains a frame pointer for a frame queued for transmission over the PCI interface to the PCI host.

Abstract: A method and arrangement for maintaining a time order of entries in a memory determines a row in which the entry will be stored, the memory being logically divided into rows and columns. The columns are arranged sequentially in each row from the newest to the oldest. Once the row in which the entry will be stored is determined, the entry is stored in that row in the column (or entry location) that is the newest column. The entry that was previously in the newest column is shifted to the next older column, and the entry that was previously in the next older column is shifted to the next most older column, etc. If a row is completely filled prior to the writing of a new entry, then the entry in the oldest column is removed from the memory and the other entries shifted.

Abstract: An integrated multiport switch (IMS) for a data network has a management port for direct communication with an external management agent. The switch, which is integrated into a single chip, includes a management interface that comprises logic circuit elements. This interface acts as a virtual physical layer for both the media access controller (MAC) at the management port and the MAC at the external management agent. The latter may be located on the same circuit board as the IMS chip. PHY devices for these MACs are eliminated while the collision signal and carrier sense signal generation functions are maintained. The PHY devices are replaced by a logic interface while permitting use of the standard Simplified Network Management Protocol (SNMP) software for the interfacing operations. No modification of MAC software is required.

Abstract: A driver having a switchable gain including a first circuit connected to a potential source, an input node receiving an input current, and an output node and operable in both low and high transmission frequency modes, and a second circuit connected to the potential source and a node of the first circuit and operable in only the high transmission frequency mode. In the low transmission frequency mode, the potential source is at a first level and the first circuit receives the input current and provides a first output current with a first current gain to the output node. In the high transmission frequency mode, the potential source is at a second, lower level and the first and second circuits receive the input current and provide a second output current, less than the first output current, with a second current gain, lower than the first current gain, to the output node.

Abstract: A novel auto-negotiation system capable of performing auto-negotiation using negative link pulses. The auto-negotiation system operates in a network transceiver for interconnecting multiple hub communication devices having different operating speeds and link partners provided on a transmission medium. The network transceiver comprises physical layer devices for supporting data exchange between the hub devices and the link partners, and an auto-negotiation device that transmits and receives link pulses of a prescribed polarity carrying auto-negotiation information to and from the link partners to select a mode of communication between the hub devices and the link partners. A reverse polarity detection and correction circuit is provided for supporting auto-negotiation operations when link pulses received from a link partner have a reverse polarity.

Abstract: A method and arrangement for transmitting multiple copies of a frame from a network switch in a packet switched network stores a single copy of the frame received at the switch into external memory. The frame is stored at a location in memory pointed to by a frame pointer. In queuing multiple transmissions of the stored frame in the switch, the frame pointer, and not the frame itself, is replicated and queued for transmission in the network switch.

Abstract: A method and arrangement for initiating forwarding of data from a device having multiple receive and transmit ports as a function of the data received at the device includes a plurality of ports for receiving and transmitting data. A port vector FIFO forwards a data identifier to initiate forwarding from at least one of the ports of a received set of data. A holding area is controlled by the port vector FIFO and receives data identifiers and holds these data identifiers until released by the port vector FIFO. The release of a data identifier initiates the forwarding of the data, and each data identifier uniquely identifies each set of data received at the device. The port vector FIFO, upon receiving a data identifier, uses the data identifier to determine the receive port that is receiving the set of data identified by the data identifier.

Abstract: A data communication device having multiple ports is provided with an auto-negotiation system for performing auto-negotiation with multiple link partners connected to the ports. The auto-negotiation system has a memory and an auto-negotiation unit including transmit, receive and arbitration state machines for performing transmit, receive and arbitration state diagrams compliant with the IEEE 802.3 Standard. The auto-negotiation unit operates in a time-division multiplexing mode using successive time slots for supporting auto-negotiation operations for different ports. The memory is used for storing state diagram variables for a port in a time interval between the time slots assigned to that port.

Abstract: An interface device enables an external device connected to a network switch to be disabled. The interface device receives and transmits data to an external device which makes data forwarding decisions. When a disable signal is received by the network switch, the disable signal is transmitted to the external device over an existing data path. The external device returns an acknowledgement signal over an existing path to the switch. A timer is included as a failsafe mechanism in case the external device does not return an acknowledge signal. The timer waits a predetermined period of time and continues the shut down of the network switch as if the acknowledge signal was received.

Abstract: An integrated multiport switch (IMS) in which one combinational logic and register arrangement is provided for executing similar media access control (MAC) functions for a plurality of switch ports. The current access state at each of a plurality of switch ports is maintained at a single state storage location, whereby access of a stored port MAC state and update thereof is simplified. Access to state storage in coordination with the single common combinational logic and register arrangement enables MAC functions for each of the plurality of ports to be performed on a time shared basis to maximize efficiency of use of chip resources and architecture space.

Abstract: An interface for use in a data forwarding device is connected between the receive ports and transmit ports of a device. The interface ensures that data being forwarded from a receive port to a transmit port has actually been received. The interface includes a queuing circuit and a de-queuing circuit. The queuing circuit receives data from the receive port, identifies the receive port, counts the data received, and buffers the data. The de-queuing circuit retrieves the buffered data at a scheduled time based on the receive port's mode, and forwards the data to a transmit port provided that the amount of data received by the queuing circuit is at least as great as the amount of data already forwarded by the de-queuing circuit plus a threshold safe level amount of data.

Abstract: An interface located on a network switch transmits header information to an external device that makes data forwarding decisions. The interface receives and transmits header information that includes the source and destination address of the data. The external device generates data forwarding information and transmits the information back to the switch via the interface device. The network switch uses the information obtained via the interface and forwards the data packets to the appropriate destination.

Abstract: A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.

Abstract: An arrangement and a method of maintaining a count of the number of copies of a frame that have been transmitted from a network switch uses a cache memory to store the number of copies of a frame to be transmitted from the network switch. A queue is used to queue entries that indicate the transmission of a copy of a frame, and these queued entries are released to a buffer manager. Whenever a transmission is made of a copy of this frame, and the buffer manager examines the entry indicating this transmission after the entry leaves the queue, the buffer manager searches for a corresponding entry in the cache memory and changes the copy number (i.e., the count of the number of transmissions) of that frame in the cache memory.