Patents by Inventor Thomas J. Schaefer

Thomas J. Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5956257
    Abstract: A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: September 21, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Arnold Ginetti, Thomas J. Schaefer, Robert D. Shur, Christopher H. Kingsley
  • Patent number: 5787010
    Abstract: A circuit optimization method in which a set of cost functions are stored for each node that indicate the cost of getting signals to that node and the cost of a gate at that node. By "cost", is meant some figure of merit, such as: the maximal delay for a signal to arrive at a node G; or the area of the elements needed to produce the signal at node G. These cost functions enable the circuit to be optimized without the need for a pattern library and the pattern matching process that is typical of other optimization processes, such as the DAGON Node Tiling Procedure.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: July 28, 1998
    Inventors: Thomas J. Schaefer, Robert D. Shur
  • Patent number: 5617325
    Abstract: A method for predicting circuit interconnect delays in circuits of the type that have a driving device attached to an input node of a network having a plurality of nodes, with the driving device changing states from time to time so as to impose on the network a voltage different from the previous voltage of the network. The method includes the steps of estimating the waveform on the input node and predicting the waveforms on other nodes of the network on the basis of the estimated input node waveform.
    Type: Grant
    Filed: September 4, 1992
    Date of Patent: April 1, 1997
    Assignee: VLSI Technology, Inc.
    Inventor: Thomas J. Schaefer
  • Patent number: 5402357
    Abstract: In a computer aided design system, a netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The automatic circuit layout synthesis process begins by assigning an initial capacitance value to each node. Next, a routing difficulty value is computed, this value comprises a sum of routing difficulty values associated with each of the nodes in the integrated circuit. Capacitance values for the integrated circuit are then adjusted so as to reduce the computed routing difficulty. Finally, the netlist and adjusted capacitance values are passed to a silicon compiler for automatic placement and routing of a circuit having capacitance values not exceeding the adjusted capacitance values.
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: March 28, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Thomas J. Schaefer, Robert D. Shur
  • Patent number: 5402356
    Abstract: A buffer circuit for fanning out a source signal to a plurality of terminals of specified polarities in accordance with specified time constraints is designed by an automated method in which a circuit template is specified in terms of a tree structure. The terminals are ordered in increasing order of required arrival times of the source signal at each of the terminals. A first terminal in a resulting order is assigned to a highest-level potential terminal site of a same polarity as said first terminal, and buffers on a signal path between said first terminal and the source signal are sized so as to satisfy, if possible, a required arrival time of the source signal at said first terminal. So long as required times of arrival are met, additional terminals are placed in like manner.
    Type: Grant
    Filed: April 2, 1992
    Date of Patent: March 28, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Thomas J. Schaefer, Robert D. Shur
  • Patent number: 5369022
    Abstract: The present invention provided a method for protecting a crop from herbicidal injury by incorporating genetic resistance into the crop in combination with treating seed of the crop with a chemical safener.
    Type: Grant
    Filed: September 17, 1993
    Date of Patent: November 29, 1994
    Assignee: American Cyanamid Company
    Inventors: Keith E. Newhouse, Thomas J. Schaefer
  • Patent number: 5348230
    Abstract: A nozzle for use in a foam gun is designed so that the ports for the two materials both enter the flow passage in the same plane. This serves to eliminate lead/lag flow conditions which result in portions of the material being off-ratio. Counterbored or milled slots encircle the angled sealing surface with the slots machined in from alternating edges of the surface communicating with the respective flow passages for the two (or more) materials.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: September 20, 1994
    Assignee: Graco, Inc.
    Inventors: Timothy L. Mullen, Thomas J. Schaefer, Tera D. McCutcheon
  • Patent number: 5290753
    Abstract: The present invention provides a method for protecting or preventing a crop from injury due to the application of a combination of compounds by altering the susceptibility of the crop by incorporating a gene resistant to inhibition by at least one of the compounds in the combination into the genome of the crop.
    Type: Grant
    Filed: May 12, 1992
    Date of Patent: March 1, 1994
    Assignee: American Cyanamid Company
    Inventors: Keith E. Newhouse, Thomas J. Schaefer, Gail E. Cary
  • Patent number: 5197015
    Abstract: In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: March 23, 1993
    Assignee: VLSI Technology, Inc.
    Inventors: Mark R. Hartoog, Thomas J. Schaefer, Robert D. Shur
  • Patent number: 5154532
    Abstract: The reciprocating pump shaft is joined to a reciprocating motor shaft by the coupling of this invention. The pump shaft is provided with a knob-like end having a chamfered angle between the knob and a reduced diameter section adjacent the knob. A two piece annular collar that's about the chamfered shoulder and the reduced diameter section and the collar is provided with a chamfered shoulder having a slight angular mis-match with the shaft shoulder. A nut draws the pump shaft upwardly against the end of the motor shaft and is tightened to the point where the pre-load between the two shafts is greater than the alternating load imposed by the motor.
    Type: Grant
    Filed: May 14, 1990
    Date of Patent: October 13, 1992
    Assignee: Graco, Inc.
    Inventors: Thomas J. Schaefer, Calvin S. Hulburt
  • Patent number: 5068812
    Abstract: A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluated. A second list is formed of each component and its corresponding output signals. The external input signals are also listed. Each external input signal is tested for change from a previous evaluation and, if so, the corresponding components in the re-evaluation list are marked for reevaluation. Each component, in levelized order, is then tested to determine whether that component is marked for re-evaluation and, if so, that component is re-evaluated and unmarked, and each signal in the component output signal list which has a non-empty re-evaluation list is tested to determine if the value of the signal has changed since the previous evaluation and, if so, all of the components in that signal's reevaluation list are marked for re-evaluation.
    Type: Grant
    Filed: July 18, 1989
    Date of Patent: November 26, 1991
    Assignee: VLSI Technology, Inc.
    Inventors: Thomas J. Schaefer, Robert D. Shur
  • Patent number: 5062067
    Abstract: A simulator for a levelized logic circuit reduces the number of evaluations required. The simulator associates certain lists of signals, called fences, with each component of a logic circuit. A fence is evaluated to determine whether it is active or inactive. Active fences contain signals which have charged since a previous evaluation. Components for active fences are then evaluated by the simulator. Fences are formed by starting with a seed set of signals. If all of the input signals to a component are in one or more fences, a final fence for a component is formed which is the union of the one or more fences. Only signals which can cause an output change on a component are included in fences.
    Type: Grant
    Filed: March 15, 1989
    Date of Patent: October 29, 1991
    Assignee: VLSI Technology, Inc.
    Inventors: Thomas J. Schaefer, Robert D. Shur
  • Patent number: 4427153
    Abstract: A plural component dispensing nozzle having internal passages for the introduction of at least two components for mixing and dispensing, and having a one piece mixing chamber with impingement orifices axially spaced along the chamber, and having formed as a part thereof sealing flanges to develop the fluid flow passages into the mixing chamber, and to provide an isolation seal between the plural components as well as fluid seals between the flow passages and the nozzle.
    Type: Grant
    Filed: August 16, 1982
    Date of Patent: January 24, 1984
    Assignee: Graco Inc.
    Inventor: Thomas J. Schaefer
  • Patent number: D346729
    Type: Grant
    Filed: February 24, 1993
    Date of Patent: May 10, 1994
    Assignee: Graco Inc.
    Inventors: Thomas J. Schaefer, Scott A. Olson, Tera D. McCutcheon, Timothy L. Mullen