Abstract: At least one of the wireless devices of a wireless network attempts to reestablish communications with a separated wireless device. Further, the separated wireless device may also attempt to reestablish communication with the wireless network. At least two of the wireless devices may separate from the wireless network to form an alternate wireless network separate from the wireless network. In such case, the at least two wireless devices of the alternate network may rejoin the wireless network after the separation. The wireless devices may establish the wireless network when proximate to one another and operating at a lower power level while continuing operation at a higher power level. The wireless devices establish the wireless network when in a first proximity to one another and continue to communicate while in a second proximity to one another.

Abstract: In an exemplary embodiment, a multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. A direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output. A multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. A multi-rate digital data filter receives the converted digital data and produces a filtered digital output. An output scaler receives the filtered digital output and produces a scaled and filtered digital output. Finally, an adder combines the scaled and filtered digital output with a center frequency input and produces the converted output.

Abstract: A multi-rate data modulation circuit includes a multi-rate data conversion circuit and a modulator such as a direct digital synthesis circuit. The multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. The direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output. The multi-rate data conversion circuit may include a multi-rate converter, a multi-rate digital data filter, an output scaler and an adder. The multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. The multi-rate digital data filter receives the converted digital data and produces a filtered digital output. The output scaler receives the filtered digital output and produces a scaled and filtered digital output.

Abstract: A low power wireless communication (personal LAN) system includes a plurality of wireless devices with each wireless device including a radio transceiver. The radio transceiver may take the form of an insertable card that fits within a slot in the wireless device. The plurality of wireless devices establishes a wireless network with at least two of the plurality of wireless devices share beaconing responsibilities to coordinate operation of the wireless network. The beaconing responsibilities may be shared on a round robin basis or may be shared according to the operating characteristics of the wireless devices with some wireless devices assuming greater beaconing responsibilities than other of the wireless devices. One of the plurality of wireless devices may separate from the wireless network to become a separated wireless device. In such case, at least one of the wireless devices attempts to reestablish communications with the separated wireless device.

Abstract: An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse.