Patents by Inventor Thomas J. Shepherd

Thomas J. Shepherd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10769013
    Abstract: Various embodiments provide for caching of error checking data for memory having inline storage configurations for primary data and error checking data for the primary data. In particular, various embodiments described herein provide for error checking data caching and cancellation of error checking data read commands for memory having inline storage configurations for primary data and associated error checking data. Additionally, various embodiments described herein provide for combining/canceling of error checking data write commands for memory having inline storage configurations for primary data and associated error checking data.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: John M. MacLaren, Landon Laws, Carl Nels Olson, Thomas J. Shepherd
  • Patent number: 10642684
    Abstract: Various embodiments described herein provide for grouping read-modify-writes (RMWs) such that multiple RMW command sequences can be executed (or rearranged in the command queue) in an interleaved manner rather than being executed in order. In particular, various embodiments described herein split the read and write components (commands) of multiple RMW command sequences, group the read components in the command queue to execute consecutively, and group the write components in the command queue to execute consecutively.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: John M. MacLaren, Anne Hughes, Thomas J. Shepherd, Carl Nels Olson
  • Patent number: 10275306
    Abstract: A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John MacLaren, Carl Olson, Jerome J. Johnson, Thomas J. Shepherd
  • Publication number: 20140055292
    Abstract: An apparatus for sharing embedded analog-to-digital conversion resources across multiple hardware and software sample conversation queues includes an analog front end, a least one FIFO buffer, a plurality of configuration registers and a sequencer. The sequencer admits a higher priority hardware stepping sequence until the higher priority stepping sequence is completed. After completion, the apparatus reverts to completing pending conversions.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 27, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas J. Shepherd, Vijaya B. P. Sarathy
  • Patent number: 8643523
    Abstract: An apparatus for sharing embedded analog-to-digital conversion resources across multiple hardware and software sample conversation queues includes an analog front end, a least one FIFO buffer, a plurality of configuration registers and a sequencer. The sequencer admits a higher priority hardware stepping sequence until the higher priority stepping sequence is completed. After completion, the apparatus reverts to completing pending conversions.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas J. Shepherd, Vijaya B P Sarathy
  • Patent number: 7280116
    Abstract: Methods and systems are disclosed for preprocessing video display pixel data. A preprocessor is provided with a selectable gamma correction mode and a selectable palette lookup mode. In palette lookup mode, a LUT memory area is used for performing a palette lookup for each of the red, green, and blue components of video pixel data, concatenating the paletted red, green, and blue components, and outputting paletted preprocessed pixel data. In gamma correction mode, the preprocessor uses the same LUT memory area for performing gamma correction on each of the red, green, and blue components of video pixel data, concatenating the gamma-corrected red, green, and blue components, and outputting a gamma-corrected preprocessed pixel data.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: October 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas J. Shepherd, Donald Richard Tillery, Jr., Moslema Sharif, Alok Mishra
  • Patent number: 6274100
    Abstract: A process irradiator includes a heavily shielded, generally cylindrical, housing with a heavily shielded top. A radiation source includes source elements in several tubes extending from the top into a shielded storage cask below the center of the housing floor. A circular track concentrically positioned relative to the track guides a motor-driven carousel carrying a number of turntables which carry material to be irradiated, the turntables being rotatable on their axes. A heavy shielded door provides access to the turntables which are successively rotated on the carousel to a position adjacent the door opening. A lifting structure on the top includes two or more lifting devices which permit selective lifting of the source elements from the storage cask into the housing. Interlock controls prevent the door from opening and the carousel from rotating unless all source elements are stored in the storage cask.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: August 14, 2001
    Assignee: J.L. Shepherd & Associated
    Inventors: Joseph L. Shepherd, Thomas J. Shepherd