Abstract: An integrated circuit having a central built-in self-test unit (BIST) that uses internal scan chains for testing embedded memory modules. The embedded memory modules receive address and data signals from a set of input flip-flops configured to form a scan chain. The BIST is coupled to an input scan chain and includes a pattern generator to shift a test pattern into the input scan chain for testing the embedded memory modules. Output flip-flops capture data from the embedded memory modules are also configured as a scan chain. The BIST includes address control logic to bypass the normal addressing logic of the embedded memory module when the BIST operates is operating in a memory test mode.

Abstract: An improvement in a switching state retention circuit of adding a shunt capacitance across an inverter output in a selectable feedback loop. The circuit has a controlled inverter connected to both the selectively connected feedback loop and an output inverter. The shunt capacitance is across an inverter in the feedback loop to control propagation delay therearound without slowing state changes at the output of the circuit.