Abstract: A data separator which extracts data embedded in a read signal includes a delay circuit that is controlled by a frequency synthesizer. The frequency synthesizer provides a write clock during write operations. A controlled oscillator included in the frequency synthesizer resides on a common integrated circuit with the delay circuit. Because component fabrication variations tend to track on a common integrated circuit, the frequency synthesizer compensates for fabrication variations in the delay circuit, thereby producing an accurate delay interval.

Abstract: A data separator for use in extracting data from a read signal includes a restart circuit. The data separator is comprised of a controlled oscillator, a delay circuit, a restart circuit, a phase detector and a data extractor. The delay circuit delays the read signal by an interval approximately equal to the time required to start the controlled oscillator after assertion of the start signal. Accordingly, the oscillator starts in-phase with the delayed read signal. In one embodiment of the present invention, the delay interval of the delay circuit is controlled by a frequency synthesizer which generates a write clock during write operations.