Patents by Inventor Thomas J. Somyak

Thomas J. Somyak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5860100
    Abstract: A L2 (high-level) cache according to the present invention implements an efficient pipelined algorithm for flushing the high-level cache and back-invalidating a L1 (low-level) cache. Initially, an address calculation stage calculates the address of a directory entry contained in an array of directory entries every clock cycle. Connected to this address calculation stage is a directory entry lookup stage. The directory entry lookup stage receives an address from the address calculation stage and retrieves the directory entry to be modified from the array of directory entries. Finally, a directory entry modification stage, connected to the directory entry lookup stage, receives the directory entry from the directory entry lookup stage. The directory entry modification stage first looks to see if the directory entry is not marked as invalid. If the directory entry is already marked as invalid, no further processing need be performed on the directory entry.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: January 12, 1999
    Assignee: International Business Machines Corporation
    Inventors: Kurt Alan Feiste, Thomas J. Somyak
  • Patent number: 5832276
    Abstract: A L2 cache for resolving collisions between processor request originating from a processor and system request originating from a computing unit attached to the system bus is provided. First, the L2 cache snoops a system request to access a shared resource. This shared resource is often an area of main memory contained in the L2 cache. Next, the L2 cache receives a processor request to access the shared resource also. The L2 cache will delay sending an acknowledge signal to the processor. The L2 cache then makes a determination as to whether the address and system request type must be sent to the processor. If data associated with the system request would alter a line in a L1 cache associated with the processor, a retry signal is sent to the processor. If the system request would not alter a line in the L1 cache, the L2 cache will wait until the system request finishes accessing the shared resource to process the processor request, thereby avoiding the sending of a retry signal to the processor.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: November 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: Kurt Alan Feiste, Thomas J. Somyak