Abstract: A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Abstract: An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication between the chips has to be accomplished by switching technology internal to the chips. The switching technology employing programmable cross-point switches; i.e. hardware elements with input, output and command ports which propagate signals from the input ports to the output ports following a given permutation determined by values on the command port. The ASIC chip contains an instruction memory to program the logic elements thereof. A conveyor belt based implementation of the programmable cross-point switches provides reduced command bit requirements.

Abstract: A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Abstract: Method, system, and program product for expanding the effective capacity of embedded memory by storing data in a compressed form and reading the data out with subsequent data decompression, including adaptive decompression and data conversion. The system and method for compression and decompression of HDL code between HDL code storage and HDL code processing for simulation of a device or system.

Abstract: An ASIC based hardware accelerated simulation engine accelerates the process of logic verification of integrated circuit designs utilizing a field of ASIC chips. The ASIC chips are interconnected by direct connections, with the communication between these chips has to be accomplished by switching technology internal to the chips. The switching technology employs programmable cross-points, that is, hardware elements with input, output and command ports. The programmable cross-points propagate signals from their input ports to their output ports following a given permutation determined by the values on the command port. To program the various logic elements of ASIC chip, the ASIC chip contains an instruction memory. This invention provides a conveyor belt based implementation of the programmable cross-point that has reduced command bit requirements compared to the prior art solution.