Patents by Inventor Thomas Jaeschke

Thomas Jaeschke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for polishing a semiconductor wafer
    Patent number: 8157617
    Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: April 17, 2012
    Assignee: Siltronic AG
    Inventors: Clemens Zapilko, Thomas Jaeschke, Makoto Tabata, Klaus Roettger
  • Integrated, continuous method for the production of molecular single-component percursors having a nitrogen bridging function
    Patent number: 7683197
    Abstract: The invention relates to a method for the regeneration of a reactor and the use of said method for the improved performance of production processes for desired products.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: March 23, 2010
    Assignee: Max-Planck-Gesellschaft zur Forderung der Wissenschaften EV
    Inventors: Grigorios Kolios, Thomas Jäschke, Martin Jansen
  • Method For Polishing A Semiconductor Wafer
    Publication number: 20100056027
    Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.
    Type: Application
    Filed: August 18, 2009
    Publication date: March 4, 2010
    Applicant: SILTRONIC AG
    Inventors: Clemens Zapilko, Thomas Jaeschke, Makoto Tabata, Klaus Roettger
  • High temperature-stabile silicon boron carbide nitride ceramics comprised of silylalkyl borazines, method for the production thereof, and their use
    Patent number: 7148368
    Abstract: The present invention concerns a process for producing silylalkylboranes containing the structural feature Si—C—B, new molecular silylalkylboranes, new molecular silyalkylborazines, new oligoborocarbosilazanes and polyborocarbosilazanes, a process for their production and their use as well as silicon boron carbide nitride ceramics and a process for their production.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: December 12, 2006
    Assignee: Max-Planck-Gesellschaft zur Forderung der Wissenschaften e.V.
    Inventors: Martin Jansen, Thomas Jäschke
  • Method for polishing a semiconductor wafer
    Patent number: RE44986
    Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Siltronic AG
    Inventors: Clemens Zapilko, Thomas Jaeschke, Makoto Tabata, Klaus Roettger