Abstract: An image signal processor, comprising an input module for obtaining input data from a camera, whereby the camera is arranged to capture a representation of a real-world environment. The image signal processor further comprises at least one adjustment module for compressing the input data and producing compressed input data, and a localization and mapping module arranged to generate one or more data points from the compressed input data. The image signal processor also comprises an output module for outputting at least the one or more data points.

Abstract: An image signal processor, comprising an input module for obtaining input data from a camera, whereby the camera is arranged to capture a representation of a real-world environment. The image signal processor further comprises at least one adjustment module for compressing the input data and producing compressed input data, and a localization and mapping module arranged to generate one or more data points from the compressed input data. The image signal processor also comprises an output module for outputting at least the one or more data points.

Abstract: When performing “time warp slice” rendering for a virtual reality display, the application rendering (30) of the images required for the application that requires the virtual reality display is synchronised (35) to the display frame rate and treated as a “normal” priority task (51) in terms of its scheduling on a host processor. The time warp slice rendering (50) to render the time warp “slices” into the display buffer (21) of the display (4) for scanning out (23) as the display panel is being refreshed is effected as a “real time” priority task (58). To do this, the rendering task setup processing that must be performed on the host processor for that rendering task is scheduled using an earliest deadline first scheduling policy and is synchronised (52) to specific, recurring display events (53) that allow the “real time” priority time warp slice rendering task setup processing on the host processor to be triggered at specific points in the scan out period (23) of the display (4).

Abstract: A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller. The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

Abstract: A graphics processing unit comprises a programmable execution unit executing graphics processing programs for execution threads to perform graphics processing operations, a local register memory comprising one or more registers, where registers of the register memory are assignable to store data associated with an individual execution thread that is being executed by the execution unit, and where the register(s) assigned to an individual execution thread are accessible only to that associated individual execution thread, and a further local memory that is operable to store data for use in common by plural execution threads, where the data stored in the further local memory is accessible to plural execution threads as they execute. The programmable execution unit is operable to selectively store output data for an execution thread in a register(s) of the local register memory assigned to the execution thread, and the further local memory.

Abstract: A graphics processing unit comprises a programmable execution unit executing graphics processing programs for execution threads to perform graphics processing operations, a local register memory comprising one or more registers, where registers of the register memory are assignable to store data associated with an individual execution thread that is being executed by the execution unit, and where the register(s) assigned to an individual execution thread are accessible only to that associated individual execution thread, and a further local memory that is operable to store data for use in common by plural execution threads, where the data stored in the further local memory is accessible to plural execution threads as they execute. The programmable execution unit is operable to selectively store output data for an execution thread in a register(s) of the local register memory assigned to the execution thread, and the further local memory.

Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller. The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

Abstract: A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

Abstract: A graphics processing apparatus performs tile based compositing operations. Tile metadata includes flag data, such as transparency and/or intensity flag data, indicating whether a given input graphics tile makes less than a predetermined first threshold level of contribution or more than a second predetermined threshold level of contribution to a corresponding output graphics tile. For example, if an input graphics tile is transparent, then its reading from a memory and/or subsequent processing may be suppressed. If a given input graphics tile is opaque, then underlying input graphics tiles that are obscured may have their reading and/or further processing suppressed.

Abstract: A graphics processing apparatus (2) performs tile based compositing operations. Tile metadata includes flag data (tfd), such as transparency and/or intensity flag data, indicating whether a given input graphics tile make less than a predetermined first threshold level of contribution or more than a second predetermined threshold level of contribution to a corresponding output graphics tile. For example, if an input graphics tile is transparent, then its reading from a memory (6) and/or subsequent processing may be suppressed. If a given input graphics tile is opaque, then any underlying input graphics tiles were are obscured may have their reading and/or further processing suppressed.