Patents by Inventor Thomas James Moutinho

Thomas James Moutinho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8324098
    Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 4, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Mehmet Emin Aklik, Thomas James Moutinho
  • Publication number: 20120007245
    Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Inventors: Mehmet Emin Aklik, Thomas James Moutinho
  • Publication number: 20110221031
    Abstract: A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 15, 2011
    Applicant: National Semiconductor Corporation
    Inventors: Sergei Drizlikh, Ashish Kushwaha, Thomas James Moutinho, David Tucker
  • Patent number: 7915093
    Abstract: A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: March 29, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Sergei Drizlikh, Ashish Kushwaha, Thomas James Moutinho, David Tucker